EDA Engineer

TekClap; Austin (TX); On-site; USD 120,000 - 190,000; Full time

Job summary

TekClap is seeking an experienced Staff CAD Engineer to advance GPU/SoC development efforts. The role requires deep expertise in CAD methods, full ASIC flow, and scalable EDA tool development.

Responsibilities include building CAD tools and flows, analyzing low-power design, and working with RTL, Verification, Physical Design, and Architecture teams to resolve complex challenges. A strong communication skillset is essential.

Qualifications

• 6+ years of CAD engineering or design enablement experience for ASIC/GPU/SoC projects.
• Deep understanding of the complete ASIC design flow: RTL, verification, synthesis, physical design, timing, power, and signoff.
• Experience with low-power design tools and methodologies such as PrimePower, PowerArtist, Joules, RTL Architect, or similar.
• Hands-on experience with EDA tools from Synopsys, Cadence, or Mentor Graphics.
• Experience with EMIR analysis tools such as RedHawk, Voltus, Totem, or comparable solutions.
• Strong analytical, troubleshooting, and problem-solving skills.
• Excellent communication and collaboration abilities.

Responsibilities

• Develop and improve CAD tools, flows, and methodologies for ASIC/GPU/SoC designs.
• Support low-power design analysis, optimization, verification, and signoff processes.
• Troubleshoot and resolve complex design flow and automation challenges.
• Collaborate with RTL, Verification, Physical Design, and Architecture teams.
• Work with internal teams and EDA vendors to improve tool capabilities and design efficiency.

Skills

CAD engineering

Design methodology

Low-power design

Analytical thinking

Communication

Education

Bachelor's degree

Master's degree or PhD (preferred)

Tools

Synopsys tools

Cadence tools

Mentor Graphics tools

EMIR analysis tools (RedHawk, Voltus, Totem)

Job description

We are looking for an experienced Staff CAD Engineer to support advanced GPU and SoC development programs. The ideal candidate will have strong expertise in CAD methodologies, ASIC design flows, low-power design techniques, and EDA tool development.

Key Responsibilities

• Develop and improve CAD tools, flows, and methodologies for ASIC/GPU/SoC designs.
• Support low-power design analysis, optimization, verification, and signoff processes.
• Troubleshoot and resolve complex design flow and automation challenges.
• Collaborate with RTL, Verification, Physical Design, and Architecture teams.
• Work with internal teams and EDA vendors to improve tool capabilities and design efficiency.

Required Qualifications

• 6+ years of experience in CAD Engineering, Design Methodology, or Design Enablement for ASIC, GPU, CPU, or SoC projects.
• Strong understanding of the complete ASIC design flow, including RTL, verification, synthesis, physical design, timing, power, and signoff.
• Experience with low-power design tools and methodologies such as PrimePower, PowerArtist, Joules, RTL Architect, or similar tools.
• Hands-on experience with EDA tools from Synopsys, Cadence, or Mentor Graphics.
• Experience with EMIR analysis tools such as RedHawk, Voltus, Totem, or comparable solutions.
• Strong analytical, troubleshooting, and problem-solving skills.
• Excellent communication and collaboration abilities.

Education

• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
• Master's degree or PhD is a plus.