Senior Power Integrity CAD Engineer: Signoff Innovator

NVIDIA; Santa Clara (CA); On-site; USD 196,000 - 368,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Power Integrity Methodology CAD Engineer in Santa Clara, CA to develop rail analysis methodologies and signoff processes for advanced NVIDIA chips.

You will drive innovative EMIR analysis workflows, collaborate with hardware and design teams, and craft scalable toolchains across multiple projects. A Master’s degree and 10+ years in EMIR are required, with strong scripting and programming skills.

Qualifications

• Master's degree or equivalent experience in Electrical Engineering or related field.
• Minimum 10+ years of experience in EMIR flow methodology development and support.
• Strong understanding of all aspects of EMIR analysis and signoff.
• Familiar with hierarchical design approach and hierarchical signoff.
• Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.
• Ability to collaborate across teams with hardware and design teams to facilitate EMIR signoff.
• Proficiency in TCL, Perl, Python, and C++.

Responsibilities

• Develop physical design methodologies for rail analysis and signoff.
• Create unique solutions for IR analysis and signoff for NVIDIA chips.
• Craft workflows and tool methodologies for power and noise analysis across projects.

Skills

EMIR flow methodology

EMIR signoff

Cross-team collaboration

Education

Master's degree in Electrical Engineering

Tools

TCL

Perl

Python

C++

Job description

NVIDIA is seeking a Senior Power Integrity Methodology CAD Engineer in Santa Clara, CA to develop rail analysis methodologies and signoff processes for advanced NVIDIA chips.

You will drive innovative EMIR analysis workflows, collaborate with hardware and design teams, and craft scalable toolchains across multiple projects. A Master’s degree and 10+ years in EMIR are required, with strong scripting and programming skills.