Staff CAD Engineer

Canvendor; Austin (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Canvendor is seeking an experienced CAD engineer to execute the technical roadmap and contribute to designing next-generation tools, flows, and methodologies for power-efficient, scalable GPU/SoC designs.

You will collaborate across RTL, physical design, and DTCO, deliver robust automation, and drive adoption of best practices while advancing low-power enablement at scale. A strong background in power analysis and signoff is essential.

Qualifications

• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years with a Master’s Degree, or 2+ years with a Ph.D.
• 6+ years of hands-on CAD, design methodology, or design enablement for GPU, CPU, or other complex SoC programs.
• Experience with RTL and gate-level power analysis, optimization, and signoff flows (e.g., PrimePower, PowerArtist, Empower, RTL-Architect, or equivalent).
• Solid understanding of the end-to-end ASIC and design flow including RTL, verification, synthesis, physical design, timing, power, EMIR, DTCO considerations.
• Experience with CAD tools for simulation, synthesis, linting, and verification (e.g., Synopsys, Cadence, Mentor Graphics).
• Hands-on EMIR tools and methodologies, including transistor, gate, and package level analysis (Redhawk, Totem, Voltus).
• Strong analytical skills, attention to detail, and problem-solving using data-driven approaches.
• Excellent collaboration and communication skills in a fast-paced, global environment.

Responsibilities

• Execute the technical roadmap for CAD engineering and contribute to next-generation tools, flows, and methodologies.
• Help deliver automation, debug tool and flow issues, and promote best practices across design organizations.
• Support low-power design enablement at scale and contribute to power analysis, optimization, verification, and signoff while aligning with RTL, physical design, and DTCO strategies.
• Advance cross-functional collaboration, partnering with internal teams and external vendors to leverage tools and accelerate technology readiness.

Skills

CAD tools

RTL design

Power analysis

Power signoff

SoC development

Collaboration

Education

Bachelor's degree in CS/Engineering

Master's degree

PhD

Tools

Synopsys

Cadence

Mentor Graphics

EMIR tools

Redhawk

Totem

Voltus

PrimePower

PowerArtist

Empower

Job description

Execute the technical roadmap for CAD engineering and contribute to the design of next-generation tools, flows, and methodologies that enable power-efficient, scalable GPU and SoC designs across advanced process nodes

Responsibility.

• Help deliver robust automation, debug complex tool and flow issues, and help drive consistent adoption of best practices across design organizations.
• Support low-power design enablement at scale, contribute to methodologies for power analysis, optimization, verification, and signoff while aligning on close integration with RTL, physical design, and DTCO strategies.
• Help advancing cross-functional and external collaboration, partnering with internal engineering teams and external vendors to leverage tool capabilities, resolve systemic design challenges, and accelerate technology readiness.
• Take initiatives on moderate-to-complex projects, advance best practices by maintaining technical documentation and staying ahead of emerging GPU and verification technologies.

Requirements

• 6+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 4+ years of experience with a Master’s Degree, or 2+ years of experience with a Ph.D.
• 6+ years of hands-on experience with hands-on experience CAD, design methodology, or design enablement for GPU, CPU, or other complex SoC programs.
• Working knowledge and experience with low-power tools and methodologies, including RTL and gate-level power analysis, optimization, and signoff flows (e.g., PrimePower, PowerArtist, Empower, Joules, RTL-Architect, or equivalent).
• Solid understanding of the end-to-end ASIC and design flow, including RTL, verification, synthesis, physical design, timing, power, EMIR, DTCO considerations.
• Solid experience with CAD tools for simulation, synthesis, linting, and verification (e.g., Synopsys, Cadence, Mentor Graphics).
• Working knowledge and hands-on experience with EMIR tools and methodologies, including transistor, gate, and package level analysis (e.g. Redhawk, Totem, Voltus)
• Strong analytical skills, attention to detail, and problem-solving skills using data-driven approach.
• Excellent collaboration and communication skills, with the ability to navigate ambiguity and maintain ownership in a fast-paced, global environment