Senior Power Architect for AI-CPU SoC Power & Performance

Ampere; Santa Clara (CA); Presencial; USD 280.000 - 420.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Premium medical insurance

401K retirement plan

Unlimited flextime

Paid holidays

Descripción de la vacante

Ampere is seeking a Distinguished Power Architect to lead power modeling, analysis, and optimization across CPU, AI accelerator, and SoC blocks. You will work across architecture, RTL, firmware, and silicon to drive power-conscious design decisions.

The role emphasizes pre- and post-silicon power analysis, power management features, and impactful workload characterization. Strong CMOS fundamentals and scripting skills are essential, with extensive experience in power-related tools.

Formación

• Experience in semiconductor power analysis, modeling, and optimization.
• Strong CMOS power fundamentals and power-reduction techniques.
• Knowledge of CPU, AI accelerator, memory, I/O, interconnect workloads.

Responsabilidades

• Define power targets, budgets, operating points, and optimization strategies for CPU, AI accelerator, and SoC blocks.
• Develop and maintain architectural, activity-based, RTL, gate-level, emulation, and silicon power models.
• Set up and run RTL- and gate-level power analysis; develop benchmarks and tests; review results for opportunities across design stages.
• Characterize workloads to identify power and performance bottlenecks across domains.
• Drive power/performance/area/thermal tradeoff studies and power convergence across design phases.
• Develop automation and data-processing flows using Python, TCL, Perl, or similar languages.

Conocimientos

Power modeling

Power optimization

Workload characterization

Python scripting

CMOS fundamentals

Analytical skills

Educación

Bachelor's degree in Electrical Engineering

Herramientas

Spyglass

Power Artist

Joules

PrimePower

Descripción del empleo

Ampere is seeking a Distinguished Power Architect to lead power modeling, analysis, and optimization across CPU, AI accelerator, and SoC blocks. You will work across architecture, RTL, firmware, and silicon to drive power-conscious design decisions.

The role emphasizes pre- and post-silicon power analysis, power management features, and impactful workload characterization. Strong CMOS fundamentals and scripting skills are essential, with extensive experience in power-related tools.