Lead SoC Power Management Architect for Energy-Efficient AI

Ampere; Santa Clara (CA); On-site; USD 226,000 - 339,000; Full time

Benefits offered by this job

Health insurance

Unlimited flextime

Paid holidays

Job summary

Ampere is seeking a Sr. Principal SoC Power Management Architect to lead architecture across SoC power management, collaborating with product and cross-functional teams to deliver energy-efficient CPU designs.

You will translate product goals into formal specifications and drive capabilities with global teams to meet performance and energy targets. Ideal candidates have 8+ years in power architecture and SoC low-power work, with RTL familiarity, DVFS/power-state control experience, and a track

Qualifications

• 8+ years of proven, hands-on power architecture and SoC low-power expertise.
• Deep HW development experience from specification to integration of low-power features.
• Power optimization expertise with data-driven validation of impact.
• Expert knowledge of SoC low-power modes, states, wake-up latency, retention.
• Ownership of SoC-level low-power management flows and sequencing.
• Cross-functional leadership with firmware/software/verification teams.
• Familiar with SW/FW; Microcontrollers; HW/SW Co-Design; ARM Architecture; Power States

Responsibilities

• Own end-to-end power management architecture; translate goals into SoC/IP requirements.
• Drive SoC and subsystem power management architecture with product teams.
• Assess and expand IP power capabilities; identify gaps and define features.
• Make HW/SW/FW trade-offs for feasible, high-performance power solutions.
• Provide technical direction and architecture reviews; lead toward Lead Power Management Architect.
• Enable HW-SW codesign and ensure integration matches architecture.
• Provide direction to verification teams for architecture definition and Si delivery.

Job description

Ampere is seeking a Sr. Principal SoC Power Management Architect to lead architecture across SoC power management, collaborating with product and cross-functional teams to deliver energy-efficient CPU designs.

You will translate product goals into formal specifications and drive capabilities with global teams to meet performance and energy targets. Ideal candidates have 8+ years in power architecture and SoC low-power work, with RTL familiarity, DVFS/power-state control experience, and a track