Principal Power Architect: AI/CPU Power & Performance Lead

Ampere; Portland (OR); On-site; USD 182,000 - 273,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

401K retirement plan

Unlimited flextime

Job summary

Ampere is seeking a Principal Power Architect to drive power modeling, analysis, optimization, management, convergence, and validation across CPU, AI accelerator, memory, I/O, and interconnect designs.

The role spans architecture, microarchitecture, RTL, implementation, firmware, validation, and silicon, with emphasis on turning workloads and power data into actionable design decisions.

Qualifications

• Experience in semiconductor power analysis, modeling, optimization, power management, workload characterization, or silicon validation.
• Strong CMOS power fundamentals and power-reduction techniques.
• Knowledge of CPU, AI accelerator, memory, I/O, interconnect, and processor workload behavior.

Responsibilities

• Define power targets, budgets, operating points, and optimization strategies for CPU, AI accelerator, and SoC blocks.
• Develop and maintain architectural, activity-based, RTL, gate-level, emulation, and silicon power models.
• Set up and run RTL- and gate-level power analysis, develop benchmarks and tests, and review results for opportunities at the architecture, RTL, synthesis, and implementation levels.
• Characterize CPU, memory, PCIe, networking, storage, AI training, and AI inference workloads to identify power and performance bottlenecks.
• Drive power/performance/area/thermal tradeoff studies and power convergence across design & implementation phases.
• Develop automation, data-processing flows, dashboards, and analysis scripts using Python, TCL, Perl, or similar languages.

Skills

Python

Tcl

Perl

C/C++

Shell

SQL

Education

Bachelor's degree in a related field or higher

Job description

Ampere is seeking a Principal Power Architect to drive power modeling, analysis, optimization, management, convergence, and validation across CPU, AI accelerator, memory, I/O, and interconnect designs.

The role spans architecture, microarchitecture, RTL, implementation, firmware, validation, and silicon, with emphasis on turning workloads and power data into actionable design decisions.