Senior Power Architect: AI Compute & Power Optimization

Ampere

Portland (OR)

On-site

USD 280,000 - 420,000

Full time

20 hours ago
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Benefits offered by this job

Health insurance
401K plan
Unlimited flextime
Paid holidays

Job summary

Ampere is a semiconductor design company focused on high-performance, energy-efficient AI compute. We seek a Distinguished Power Architect to drive power modeling, analysis, optimization, and validation across CPU, AI accelerator, memory, I/O, and interconnect designs.

This role collaborates with architecture, RTL, firmware, and silicon teams to turn workload data into design decisions. Applicants should have CMOS fundamentals and extensive experience in power analysis, RTL/gate-level methods,

Qualifications

  • Experience in semiconductor power analysis and modeling.
  • Strong CMOS power fundamentals and techniques.
  • RTL and gate-level power-analysis experience.
  • Proficiency in Python and scripting for data analysis.

Responsibilities

  • Define power targets, budgets, and operating points.
  • Develop and maintain power models across CPU, AI accelerator, memory, I/O.
  • Run RTL- and gate-level power analysis and review results.
  • Characterize workloads to identify power and performance bottlenecks.
  • Drive power-management techniques including DVFS and clock gating.

Skills

Python
Tcl
Perl
C/C++
Shell
SQL

Education

Bachelor's degree in Electrical Engineering
Master's degree in Electrical Engineering
PhD in Electrical Engineering

Tools

Spyglass
Power Artist
Joules
PrimePower

Job description

Ampere is a semiconductor design company focused on high-performance, energy-efficient AI compute. We seek a Distinguished Power Architect to drive power modeling, analysis, optimization, and validation across CPU, AI accelerator, memory, I/O, and interconnect designs.

This role collaborates with architecture, RTL, firmware, and silicon teams to turn workload data into design decisions. Applicants should have CMOS fundamentals and extensive experience in power analysis, RTL/gate-level methods,

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