Senior Power Architect for AI/CPU SoC - Unlimited Flextime

Ampere; California; On-site; USD 280,000 - 420,000; Full time

Benefits offered by this job

Premium medical insurance

Dental insurance

Vision insurance

Income protection

401K retirement plan

Unlimited flextime

10+ paid holidays

Snacks and beverages

Job summary

Ampere is seeking a Distinguished Power Architect in California to drive power modeling, analysis, optimization, management, convergence, and validation across CPU, AI accelerator, memory, I/O, and interconnect designs. The role spans architecture, RTL, firmware, and silicon for high-performance, energy-efficient AI compute.

The ideal candidate turns workloads and power data into actionable design decisions, leads pre- and post-silicon power activities, and collaborates with cross-functional

Qualifications

• Experience in semiconductor power analysis, modeling, optimization, power management, workload characterization, or silicon validation.
• Strong CMOS power fundamentals and power-reduction techniques.
• Knowledge of CPU, AI accelerator, memory, I/O, interconnect, and processor workload behavior.

Responsibilities

• Define power targets, budgets, operating points, and optimization strategies for CPU, AI accelerator, and SoC blocks.
• Develop and maintain architectural, activity-based, RTL, gate-level, emulation, and silicon power models.
• Set up and run RTL- and gate-level power analysis, develop benchmarks and tests, and review results for opportunities at multiple design levels.
• Characterize workloads to identify power and performance bottlenecks.
• Drive power/performance/area/thermal tradeoff studies and power convergence across design phases.

Skills

Power analysis & modeling

Python scripting

C/C++

Power management

Workload characterization

Communication

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

Spyglass

Power Artist

Joules

PrimePower

Job description

Ampere is seeking a Distinguished Power Architect in California to drive power modeling, analysis, optimization, management, convergence, and validation across CPU, AI accelerator, memory, I/O, and interconnect designs. The role spans architecture, RTL, firmware, and silicon for high-performance, energy-efficient AI compute.

The ideal candidate turns workloads and power data into actionable design decisions, leads pre- and post-silicon power activities, and collaborates with cross-functional