Senior ASIC Validation Engineer – Networking & Chiplet SoCs

Eridu Corporation; Saratoga (CA); On-site; USD 185,000 - 250,000; Full time

Job summary

A Silicon Valley-based hardware startup is looking for a highly experienced Post-Silicon ASIC Validation Engineer. The role involves leading validation of complex networking ASICs and chiplet-based architectures. The ideal candidate has strong expertise in post-silicon validation and high-speed interconnects. This position offers a chance to work on groundbreaking technology impacting AI infrastructure. The pay range for this role is $185,000 - $250,000 per year, reflecting the contribution to innovative AI performance enhancements.

Qualifications

• Experience in post-silicon validation and bring-up of complex ASICs or SoCs.
• Hands-on experience with UCIe, PCIe and high-speed interconnect standards.
• Strong lab experience using oscilloscopes and logic analyzers.

Responsibilities

• Drive post-silicon validation and bring-up of networking ASICs and chiplet-based SoCs.
• Develop automation and test infrastructure for high-speed link and protocol validation.
• Execute validation of UCIe interfaces and die-to-die interconnects.

Skills

Post-silicon validation

Networking ASICs

Chiplet-based architectures

Python scripting

Signal integrity analysis

Education

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field

Tools

Oscilloscopes

Logic analyzers

JTAG-based debuggers

Job description

A Silicon Valley-based hardware startup is looking for a highly experienced Post-Silicon ASIC Validation Engineer. The role involves leading validation of complex networking ASICs and chiplet-based architectures. The ideal candidate has strong expertise in post-silicon validation and high-speed interconnects. This position offers a chance to work on groundbreaking technology impacting AI infrastructure. The pay range for this role is $185,000 - $250,000 per year, reflecting the contribution to innovative AI performance enhancements.