Senior ASIC Verification Engineer - Networking, Tape-Outs

Socket.dev; Wayne (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

401K matching

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Paid holidays

Vacation time

Job summary

Socket.dev seeks an experienced ASIC verification engineer to join the system-level verification team in California. You will develop verification environments and test plans for high-performance networking silicon, collaborating with architects and design engineers to drive verification closure.

With 8+ years in ASIC design/verification and strong Verilog/SystemVerilog skills, you will contribute across the lifecycle from testbench architecture to tape-out, including exposure to Ethernet/PCIe

Qualifications

• 8+ years of ASIC design/verification experience.
• Bachelor's in Engineering.
• Strong Verilog knowledge with C/C++ hands-on.
• Experience with UVM/SystemVerilog and ASIC verification flows.
• Networking protocols (Ethernet, PCIe) experience is a plus.
• Multiple ASIC tape-outs completed.

Responsibilities

• Develop complex verification environments and test plans.
• Verify high-performance network switch ASIC/FPGA end-to-end.
• Collaborate with system architects, design and verification teams; implement across verification stack.

Skills

ASIC verification

Verilog

SystemVerilog

UVM

C/C++

OOP

Networking protocols

Education

Bachelor's in Engineering

Job description

Socket.dev seeks an experienced ASIC verification engineer to join the system-level verification team in California. You will develop verification environments and test plans for high-performance networking silicon, collaborating with architects and design engineers to drive verification closure.

With 8+ years in ASIC design/verification and strong Verilog/SystemVerilog skills, you will contribute across the lifecycle from testbench architecture to tape-out, including exposure to Ethernet/PCIe