SoC Failure Analysis Lead — Hardware & Validation

Jobtailor; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Jobtailor in San Jose, CA seeks an experienced Electrical Post-Silicon Validation engineer to verify ASICs and lead failure analysis with cross-functional teams.

You will define post-silicon validation plans, capture device performance data, and advance power integrity, signal integrity, and reliability.

Proficiency in Python and C++, experience with oscilloscopes, VNA, BERT, and logic analyzers is required to drive SoC validation and observability software.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering with 6+ years of relevant experience, or advanced degrees as stated.
• Experience in post-silicon validation, SoC failure analysis, power and signal integrity.
• Proficient with high-speed mixed-signal design, DFT, SRAM design/integration.
• Experience driving SoC failure analysis efforts.
• Experience with electrical diagnostics and measurement equipment.
• Experience with high-speed interfaces.
• Software development in Python or C++.

Responsibilities

• Engage in dynamic collaboration with verification engineers, designers, and cross-functional teams.
• Ensure the successful verification and quality of the ASIC throughout its lifecycle.
• Lead and participate in failure analysis efforts, determining contributing factors and corrective actions.
• Lead activities aiming at improving product performance, yield, and reliability.
• Define, and refine post silicon validation plans covering functionality, performance characterization, and reliability.
• Capture, analyze, and interpret device performance, waveforms, eye diagrams, jitter, BER, PDN measurements, power supply stability and noise.
• Validate system-level behavior under real-world networking workloads.
• Contribute to the chip screening test and observability software library (Python, C++).

Skills

Electrical Post-Silicon Validation

SoC Failure Analysis

High-Speed Mixed-Signal Design

Python Programming

C++ Programming

Design for Test (DFT)

Power and Signal Integrity

Networking fundamentals

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's degree in Electrical Engineering or Computer Engineering

PhD in Electrical Engineering or Computer Engineering

Tools

Oscilloscopes

VNA

BERT

Logic Analyzers

Job description

Jobtailor in San Jose, CA seeks an experienced Electrical Post-Silicon Validation engineer to verify ASICs and lead failure analysis with cross-functional teams.

You will define post-silicon validation plans, capture device performance data, and advance power integrity, signal integrity, and reliability.

Proficiency in Python and C++, experience with oscilloscopes, VNA, BERT, and logic analyzers is required to drive SoC validation and observability software.