Senior PLL IC Design Architect – mmWave

Blue Origin; San Diego (CA); On-site; USD 308,000 - 431,000; Full time

Benefits offered by this job

Relocation provided

Travel up to 10%

Technical assessment interviews

Job summary

Blue Origin seeks a Senior Principal IC Design Engineer to lead PLLs and clocking in advanced CMOS/SiGe processes for mmWave RF applications. The role emphasizes high-speed PLL design, loop optimization, and close collaboration with RF/SOC architects to ensure seamless integration into space communication payloads. On-site in San Diego with limited remote flexibility.

The position requires extensive experience, leadership, and a U.S. citizenship or equivalent.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 15+ years of high-speed PLL design experience (>20 GHz).
• Experience with loop design for phase noise/jitter and optimization.
• Design of PLLs and clock distribution for RF and mmWave.
• Clock domain synchronization in multi-PLL systems.
• RF/mixed-mode modeling, verification using MATLAB/Spectre/SystemVerilog/AMS.

Responsibilities

• Lead design, development and integration of PLLs and clock distribution in CMOS FinFET and SiGe Techs.
• Use Spectre and AMS flows to develop high-performance PLLs.
• Collaborate with RF and SOC architects to define PLL requirements for RF payloads and terminals.
• Oversee layout, top-level integration, floorplanning and tape-out verification.
• Develop test plans with validation and product engineers; optimize performance and yield.
• Investigate and implement analog building blocks to improve circuit performance.
• Mentor junior engineers on best analog design practices.

Skills

PLL design

RF/mmWave experience

Clock distribution

Loop design

Mixed-signal modeling

Education

Bachelor's degree in Electrical Engineering

Tools

Spectre

AMS flows

SystemVerilog

MATLAB

Job description

Blue Origin seeks a Senior Principal IC Design Engineer to lead PLLs and clocking in advanced CMOS/SiGe processes for mmWave RF applications. The role emphasizes high-speed PLL design, loop optimization, and close collaboration with RF/SOC architects to ensure seamless integration into space communication payloads. On-site in San Diego with limited remote flexibility.

The position requires extensive experience, leadership, and a U.S. citizenship or equivalent.