Senior Principal PLL IC Design Engineer (mmWave/Space)

Socket.dev; California (MO); On-site; USD 308,000 - 431,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) with company match

Paid time off

Stock options

Job summary

Blue Origin in San Diego, CA is seeking a Senior Principal IC Design Engineer to lead PLLs and clocking systems across CMOS FinFET and SiGe processes, including mmWave work. You will partner with RF and SOC architects to optimize performance and drive successful tape-out cycles.

Relocation is provided; travel up to 10% is expected. Interviews include a technical assessment; the role is onsite with a temporary remote work exception during site development.

Qualifications

• Bachelor's degree in Electrical Engineering or related technical discipline.
• 15+ years in high-speed PLLs and LO generation at RF/mmWave frequencies.
• Experience with loop design for phase noise, spur, area and power optimization.
• Proficiency in PLLs and clock distribution for wireless/wireline apps.
• US citizen or eligible for U.S. residency.

Responsibilities

• Lead design, development and integration of PLLs and clock distribution in CMOS FinFET and SiGe technologies.
• Use Spectre and AMS flows to develop high-performance PLL circuits.
• Collaborate with RF and SOC architects to define PLL requirements for RF payloads.
• Oversee layout, integration, floorplanning, and tape-out readiness.
• Develop test plans with validation and product engineers for bring-up and yield.
• Investigate analog building blocks to enhance circuit performance.
• Mentor junior engineers on analog design practices.

Skills

PLL design

Clock distribution

RF/mmWave design

Loop design for phase noise

Spectre + AMS

SystemVerilog modeling

RF testing & verification

Analog circuit design

Education

Bachelor's degree in Electrical Engineering

MS/PhD in EE (preferred)

Tools

MATLAB

Spectre

SystemVerilog

AMS

Job description

Blue Origin in San Diego, CA is seeking a Senior Principal IC Design Engineer to lead PLLs and clocking systems across CMOS FinFET and SiGe processes, including mmWave work. You will partner with RF and SOC architects to optimize performance and drive successful tape-out cycles.

Relocation is provided; travel up to 10% is expected. Interviews include a technical assessment; the role is onsite with a temporary remote work exception during site development.