Senior PLL Design Engineer – High‑Speed Transceivers

Celero Communications, Inc.; San Jose, Irvine (CA, CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a High-Speed CMOS PLL Analog Design Engineer to deliver innovative clocking circuits for optical transceivers. You will be responsible for architecting and designing PLLs, addressing challenges in advanced node technologies, and supervising layouts produced by engineers.

A Master's degree or PhD in Electrical Engineering, coupled with over 5 years of PLL design experience, is essential. This role offers a salary between $150,000 and $250,000 annually, based on skills and experience.

Qualifications

• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of experience.
• Extensive experience with advanced node technologies (16 nm/12 nm, 7 nm, 5 nm, 3 nm, 2 nm processes).
• Deep understanding of phase noise analysis and PLL supporting circuitry.

Responsibilities

• Architect, design, and simulate analog/mixed-signal PLL building blocks.
• Supervise and verify layouts produced by layout engineers.
• Conduct performance characterization using lab equipment.

Skills

PLL design expertise

Analog circuit design

VCO and LDO experience

Cadence Virtuoso proficiency

Strong communication skills

Education

Master’s degree or PhD in Electrical Engineering

Tools

Cadence Virtuoso

MATLAB

EMX/HFSS

Job description

Celero Communications, Inc. is seeking a High-Speed CMOS PLL Analog Design Engineer to deliver innovative clocking circuits for optical transceivers. You will be responsible for architecting and designing PLLs, addressing challenges in advanced node technologies, and supervising layouts produced by engineers.

A Master's degree or PhD in Electrical Engineering, coupled with over 5 years of PLL design experience, is essential. This role offers a salary between $150,000 and $250,000 annually, based on skills and experience.