Principal PLL Design Engineer

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a High-Speed CMOS PLL Analog Design Engineer to deliver innovative clocking circuits for optical transceivers. You will be responsible for architecting and designing PLLs, addressing challenges in advanced node technologies, and supervising layouts produced by engineers.

A Master's degree or PhD in Electrical Engineering, coupled with over 5 years of PLL design experience, is essential. This role offers a salary between $150,000 and $250,000 annually, based on skills and experience.

Qualifications

• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of experience.
• Extensive experience with advanced node technologies (16 nm/12 nm, 7 nm, 5 nm, 3 nm, 2 nm processes).
• Deep understanding of phase noise analysis and PLL supporting circuitry.

Responsibilities

• Architect, design, and simulate analog/mixed-signal PLL building blocks.
• Supervise and verify layouts produced by layout engineers.
• Conduct performance characterization using lab equipment.

Skills

PLL design expertise

Analog circuit design

VCO and LDO experience

Cadence Virtuoso proficiency

Strong communication skills

Education

Master’s degree or PhD in Electrical Engineering

Tools

Cadence Virtuoso

MATLAB

EMX/HFSS

Job description

Are you a PLLDesign Engineer who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High‑Speed CMOS PLL Analog Design Engineer – a fast‑growing startup company seeking an expert in clocking circuits for next‑generation optical transceivers, high‑speed SerDes, and ADC/DAC systems.

Preferred Locations: Irvine, CA and San Jose, CA

Alternate Locations: Vancouver, BC and Ottawa, ON

Candidate will have the opportunity to architect and design PLLs for next generation transceivers.

What You Will Do:

• Understand trade‑offs between different PLL topologies (e.g., integer‑N, fractional‑N, all‑digital/ADPLL) to meet specifications for power, area, jitter, and frequency range.
• Architect, design and simulate analog/mixed‑signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, loop filters) at transistor level using tools like Cadence Virtuoso and Spectre.
• Address challenges in advanced node technologies, such as self‑heating, electromigration, VCO linearization and device‑level noise optimization.
• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies.
• Be responsible for PLL bring‑up in the lab, conducting performance characterization using state‑of‑the‑art lab equipment.
• Conduct comprehensive system‑level simulations and validation for PLL integration into advanced transceiver technologies.

What You Will Bring:

• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design and production‑level tape‑out experience.
• Must have extensive experience with advanced node technologies (16 nm/12 nm, 7 nm, 5 nm, 3 nm, 2 nm processes).
• Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs.
• Proficient in Cadence Virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system‑level modelling.
• Strong communication and documentation skills.

Salary Range

$150,000 – $250,000 Annually

The final offer will be determined based on job‑related skills, experience, qualifications, and location.

As set forth in Celero Communications, Inc.’s Equal Employment Opportunity policy, we do not discriminate on the basis of any protected group status under any applicable law.