Principal PLL Design Engineer

Celero Communications, Inc.; United States; Remote; USD 200,000 - 300,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal PLL Design Engineer to architect and implement high-speed PLLs for next‑gen optical transceivers and SerDes systems.

Responsibilities include designing and simulating analog/mixed‑signal PLL blocks, supervising layouts, and leading lab bring‑up and validation with modern equipment.

Qualifications

• Master's or PhD in Electrical Engineering with 5+ years of PLL design experience.
• Production tape-out experience and advanced node knowledge (16nm–2nm).
• Experience with phase noise, VCOs, LDOs, and PLL supporting circuitry.
• Proficient with Cadence Virtuoso and MATLAB.

Responsibilities

• Design, simulate, and verify analog/mixed-signal PLL blocks at transistor level.
• Architect PLL topologies (fractional-N, integer-N, ADPLL) to meet targets for power, area, and jitter.
• Oversee layouts and parasitic minimization with layout teams.
• Lead bring-up and characterization in lab with state-of-the-art equipment.
• Perform system-level simulations for PLL integration into transceiver tech.

Skills

High-speed PLL design

VCO design

Phase noise analysis

Cadence Virtuoso

EMX/HFSS

MATLAB

Education

Master's or PhD in Electrical Engineering

Tools

Cadence Virtuoso

EMX/HFSS

MATLAB

Job description

Principal PLL Design Engineer

Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.

What You Will Do

• Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range
• Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization
• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies
• Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
• Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies

What You Will Bring

• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience.
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs
• Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling
• Strong communication and documentation skills

Annual Base Salary Range

$200,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)