Senior Physical Design & Timing Engineer - Hybrid + Equity

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Hybrid work model

Job summary

NVIDIA Corporation is seeking a Senior Physical Design and Timing Engineer in Santa Clara, CA. You will drive high-frequency and low-power design across CPUs, GPUs, LPUs, and SoCs, collaborating with multiple teams to deliver robust tapeouts.

The role requires advanced timing knowledge, scripting skills, and hands-on experience from RTL to tapeout, with a focus on power, performance, and area optimization.

Qualifications

• BS in Electrical or Computer Engineering with 5+ years, or MS with 3+ years.
• Hands-on experience from RTL to tapeout including synthesis and ECOs.
• Proven ability to improve power, performance, and area.
• STA and timing-closure experience under PVT variations.
• Proficiency with Python, Tcl, Perl, Make, and AI/ML/DL/LLMs.

Responsibilities

• Drive physical design and timing for CPUs, GPUs, LPUs, and SoCs at block/cluster/chip levels.
• Support frontend/backend from RTL to gds2, including synthesis, floorplanning, timing, and ECOs.
• Collaborate with cross-functional teams to optimize design and signoff.

Skills

Physical design

Timing analysis

RTL to tapeout

EDA tools

Python scripting

Education

BS or MS in Electrical/Computer Engineering

Tools

EDA tools

Job description

NVIDIA Corporation is seeking a Senior Physical Design and Timing Engineer in Santa Clara, CA. You will drive high-frequency and low-power design across CPUs, GPUs, LPUs, and SoCs, collaborating with multiple teams to deliver robust tapeouts.

The role requires advanced timing knowledge, scripting skills, and hands-on experience from RTL to tapeout, with a focus on power, performance, and area optimization.