Senior Physical Design Engineer - Drive Timing & Innovation

NVIDIA Corporation; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking a motivated Physical Design Engineer to join our team in Santa Clara, CA. You will drive physical design and timing from netlist to GDS, collaborating with analog/mixed-signal teams and frontend groups to implement timing constraints and robust flows.

The role requires a BS or MS in Electrical or Computer Engineering with 6+ years (or 3+ years for MS) of experience in physical design, and proficiency with Synopsys or Cadence place-and-route tools; DFT knowledge is a

Qualifications

• BS or MS in Electrical or Computer Engineering with 6+ years (or MS with 3+ years) in physical design.
• Experienced in Synopsys or Cadence place and route, physical design and timing tools.
• Ability to form methodologies and automate flows.
• Scan insertion and DFT knowledge is a plus.

Responsibilities

• Drive physical design and timing from netlist to GDS.
• Partner with mixed signal teams to integrate Analog IOs and macros.
• Work on multi-mode and multi-corner timing closure, RC extraction, cross talk, IR drop and EM analysis.
• Work with the Front-end teams to create and update timing constraints.
• Perform physical verification DRC, ERC, LVS, antenna checks and other checks.
• Debug timing violations and implement functional, timing ECOs and perform formal verification.

Skills

Methodology development

Automation

DFT knowledge (nice to have)

Education

BS or MS in Electrical or Computer Engineering

Tools

Synopsys P&R

Cadence P&R

Job description

NVIDIA Corporation is seeking a motivated Physical Design Engineer to join our team in Santa Clara, CA. You will drive physical design and timing from netlist to GDS, collaborating with analog/mixed-signal teams and frontend groups to implement timing constraints and robust flows.

The role requires a BS or MS in Electrical or Computer Engineering with 6+ years (or 3+ years for MS) of experience in physical design, and proficiency with Synopsys or Cadence place-and-route tools; DFT knowledge is a