Senior DTCO Engineer, CPU Physical Design | Equity

NVIDIA; Santa Clara (CA); On-site; USD 136,000 - 265,000; Full time

Job summary

NVIDIA in Santa Clara, California is seeking a Senior DTCO Engineer, CPU Physical Design to join our growing team. You will evaluate advanced process technologies, perform synthesis, place-and-route, and timing analysis, and coordinate with foundry, IP, and hardware teams early in development.

You will identify bottlenecks through early pathfinding, assess technology-node scaling, and compare competitive products to guide technology choices.

Qualifications

• Master’s or Ph.D. in Electrical Engineering or related field (or equivalent).
• 5+ years of relevant experience.
• Strong background in advanced-node silicon design and physical-design methodology.
• Ability to analyze physical implementation constraints and develop technology solutions to improve PPA.
• Proficiency with Python, Tcl, Perl, or similar scripting languages, as well as AI tools.

Responsibilities

• Evaluate advanced process technologies and help shape technology choices for next-generation CPUs.
• Run synthesis, place-and-route, and static timing analysis to assess how process features affect power, performance, and area.
• Work with foundry, IP, and hardware design teams during early technology development.
• Use early pathfinding blocks to identify implementation bottlenecks and project technology-node scaling.
• Evaluate competitive products and benchmarks to understand technology and design trade-offs.

Skills

Python scripting

Tcl scripting

Perl scripting

AI tools

Education

Master’s or Ph.D. in Electrical Engineering or related field

Tools

Synthesis tools

Place-and-Route tools

STA tools

Python tooling

Job description

NVIDIA in Santa Clara, California is seeking a Senior DTCO Engineer, CPU Physical Design to join our growing team. You will evaluate advanced process technologies, perform synthesis, place-and-route, and timing analysis, and coordinate with foundry, IP, and hardware teams early in development.

You will identify bottlenecks through early pathfinding, assess technology-node scaling, and compare competitive products to guide technology choices.