Senior Physical Design Engineers

Digicomm Semiconductor INC; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Digicomm Semiconductor INC in Austin, Texas, is seeking an experienced physical design engineer to analyze designs, partition into blocks, and minimize inter-block connections. You will allocate external IPs, optimize placement, and perform PPO before CTS, followed by CTS routing and timing verification.

You will also conduct STA, LVS, DRC, ERC checks and ensure signal integrity throughout the layout. The role emphasizes thorough planning, constraint generation, and industry-standard physical

Qualifications

• Analyze the design and divide into small blocks.
• Split the circuit such that the number of connections between partitions is minimized.
• Identify appropriate places for different blocks within the chip area.
• Allocate places for external Hard IPs.
• Place and optimize the various small blocks identified during partitioning.
• Perform Post Placement Optimization (PPO) before clock tree synthesis (CTS).

Responsibilities

• Analyze the design and divide into small blocks.
• Split the circuit such that the number of connections between partitions is minimized.
• Identify appropriate places for different blocks within the chip area.
• Allocate places for external Hard IPs.
• Place and optimize the various small blocks identified during partitioning.
• Post Placement Optimization (PPO) before clock tree synthesis (CTS).
• Routing the various clock signals within the design so that the clock skew is minimized.
• Clock Tree Synthesis (CTS).
• Perform the STA across the complete design to ensure timing checks are clean.
• Constraint generation, budgeting, and timing sign-off with IR/EM analysis.
• Signal integrity checks.
• Layout vs Schematic checks (LVS), Design Rule Checks (DRC), Electrical Rule Checks (ERC).

Job description

• Analyze the design and divide into small blocks.
• Split the circuit such that the number of connections between partitions is minimized.
• Based on the design analysis identifying appropriate place for different blocks within the chip area.
• Allocating places for external Hard IPs.
• Placing and optimizing the various small blocks identified during partitioning process:
• Post Placement Optimization (PPO) before clock tree synthesis (CTS)
• Routing the various clock signals within the design so that the clock skews are optimized:
• Clock Tree Synthesis (CTS)
• Perform the STA, across the complete design to ensure that all the timing checks are clean:
• Constraint Generation
• Budgeting
• Timing Sign off, IR/EM Analysis
• Signal integrity
• Perform Physical Verification against various critical parameters & criteria:
• Layout Vs Schematic Checks (LVS)
• Design Rule Checks (DRC)
• Electrical Rule Checks (ERC)