STA Engineer

Digicomm Semiconductor INC; United States; On-site; USD 120,000 - 180,000; Full time

Job summary

Digicomm Semiconductor INC in the United States seeks an experienced timing engineer to drive timing constraint generation and STA setup across RTL and physical design. The role involves evaluating setup/hold, clock-to-q delays, and CDC issues, and delivering actionable reports for timing optimization.

You will collaborate with RTL, physical design and verification teams to ensure timing closure, address multicycle paths, false paths, and post-layout parasitics, while contributing to CTS-related

Qualifications

• 5+ years of experience in timing analysis and STA workflows.
• Proven ability to define timing constraints and drive closure.
• Experience collaborating with RTL, physical design and verification.

Responsibilities

• Timing Constraint Generation: Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
• STA Setup: Set up and configure STA tools for the analysis, including library characterization, delay models, and clock definitions.
• Timing Analysis: Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics.
• CDC Analysis: Identify and analyze asynchronous signals crossing between clock domains to ensure proper synchronization.
• MCP and False Paths: Define and analyze multicycle paths and false paths to accurately capture timing constraints.
• Timing Closure: Collaborate with RTL and physical design teams to achieve timing closure and perform ECO analysis.
• CTS: Work with CTS engineers to ensure the clock tree meets timing and minimizes skew/jitter.
• Post-Layout STA: Perform post-layout STA to account for parasitics and resolve timing violations.
• Timing Margins: Analyze margins to ensure robust operation under variations.
• Report Generation: Prepare detailed timing analysis reports with paths, violations, and optimization suggestions.
• Cross-Functional Collaboration: Collaborate with RTL, physical design, DFT and verification teams to resolve timing issues.
• Methodology Development: Contribute to STA methodologies and flows for efficiency and accuracy.

Skills

Timing analysis

STA setup

CDC analysis

Timing closure

Cross-functional collab

Tools

Cadence Encounter

Synopsys PrimeTime

Job description

• Timing Constraint Generation: Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
• STA Setup: Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions.
• Timing Analysis: Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations).
• Clock Domain Crossing (CDC) Analysis: Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues.
• Multicycle Paths (MCP) and False Paths: Define and analyze multicycle paths and false paths to accurately capture the design's timing constraints.
• Timing Closure: Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues.
• Clock Tree Synthesis (CTS): Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter.
• Post-Layout STA: Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure.
• Timing Margins: Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation.
• Report Generation: Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization.
• Cross-Functional Collaboration: Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues.
• Methodology Development: Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.