Principal Physical Design Engineer

Celero Communications, Inc.; United States; Remote; USD 200,000 - 300,000; Full time

Job summary

Celero Communications, Inc. in the United States seeks a Senior/Principal Physical Design Engineer to lead RTL-to-GDSII implementation of SoCs and complex digital blocks.

You will own floorplanning, CTS, power grid design, and signoff verification to drive tapeout readiness. You will collaborate with architects, logic designers, and analog teams, optimize timing, routing, EM/IR cleanup, and develop automated flows using Tcl/Python/Perl.

Qualifications

• 7+ to 15+ years of ASIC physical design experience.
• Deep tapeout experience in advanced technology nodes (e.g., 7nm/5nm/3nm).
• Advanced proficiency with Cadence tools (Innovus, Tempus, Voltus, Pegasus, Calibre).
• Expertise in physically aware synthesis, power-domain analysis, and EM/IR cleanup.

Responsibilities

• RTL-to-GDSII execution: own physical implementation of SoCs or complex digital blocks.
• Floorplanning, bump planning, power grid design, and CTS to optimize chip performance.
• Resolve timing, congestion, EM/IR issues with frontend designers.
• Run STA and physical verification; fix DRC/LVS violations.
• Drive automation and flow robustness with Tcl, Python, or Perl.
• Partner with architects, logic designers, and analog team for tapeout readiness.

Job description

Senior/Principal Physical Design Engineer

Core Responsibilities

• RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
• Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
• Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
• Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
• Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
• Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.

Key Qualifications

• Experience: 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).
• Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre).
• Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Annual Base Salary Range: $200,000 to $300,000 (The final offer will be determined based on job‑related skills, experience, qualifications, and location.)
celerocatsone