Principal Physical Design Engineer | Irvine, CA

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. seeks an experienced Physical Design Engineer to lead the implementation of SoCs, from floorplanning to timing closure. You will drive P&R, CTS, power planning, and signoff while collaborating with architecture, RTL, and verification teams to meet aggressive PPA targets and tapeout deadlines.

Join a fast-growing semiconductor startup that emphasizes innovation, mentorship, and cross-functional leadership in a dynamic San Jose or Irvine, CA environment.

Qualifications

• 5+ years of ASIC physical design experience.
• Tapeout experience in advanced nodes (7nm/5nm/3nm).
• Proficient with Cadence tools including Innovus, Tempus, Voltus, Pegasus, Calibre.
• Experience with physically aware synthesis, power-domain analysis, and EM/IR cleanup.

Responsibilities

• RTL-to-GDSII execution of SoCs or complex digital blocks.
• Manage floorplanning, bump planning, power grid design, and CTS.
• Resolve timing, congestion, EM/IR issues with frontend designers.
• Run STA and physical verification; fix DRC and LVS violations.
• Drive automation and flow robustness with Tcl, Python, or Perl.
• Partner with architects, logic designers, and analog design for tapeout readiness.

Skills

ASIC physical design experience

Floorplanning

Place & Route (P&R)

Static timing analysis (STA)

EM/IR cleanup

Scripting (Tcl/Python/Perl)

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Cadence Pegasus

Calibre

Job description

Company Overview

Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure.

We are seeking an experiencedPhysical Design Engineer to lead the transformation of complex circuit designs into high-quality, manufacturable silicon. In this role, you will drive all aspects of the physical implementation flow, including floorplanning, power planning, place-and-route (P&R), clock tree synthesis, timing closure, and physical verification. You will collaborate closely with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet aggressive targets for performance, power, area (PPA), signal integrity, and manufacturability. As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor products.

Locations

San Jose, CA (preferred) or Irvine, CA (HQ)

Core Responsibilities

• RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
• Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
• Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
• Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
• Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
• Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.

Key Qualifications

• Must have 5+ years of relevant ASIC physical design experience (depending on degree level).
• Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
• Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre).
• Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.

Annual Base Salary Range: $150,000 to $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

As set forth in Celero Communications, Inc.’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.