Senior ASIC Physical Design Engineer - Place & Route (Austin)

TSMC - Taiwan Semiconductor Manufacturing Company Limited; Austin (TX); Hybrid; USD 106,500 - 162,000; Full time

Benefits offered by this job

Comprehensive benefits

Extensive development opportunities

Market competitive pay

Job summary

A leading semiconductor foundry in Austin, TX is seeking a Senior Engineer, Physical Design (ASIC/SoC Place & Route). This role involves the entire APR implementation flow from RTL-to-GDS, working in a hybrid model with 4 days in the office. Candidates should have a Master’s in Electrical/Computer Science Engineering and 7+ years of industry experience, particularly with TSMC technologies. The offered compensation ranges from $106,500 to $162,000 annually, along with comprehensive benefits.

Qualifications

• 7+ years of industry experience in semiconductor manufacturing.
• Experience in block level implementation or chip integration.

Responsibilities

• Complete entire physical implementation of the block level and tapeout production chip.
• Custom Clock tree structure and Place & Route.

Skills

Netlist-GDS physical implementation experience

In-depth knowledge of major EDA tools/design flows

Perl/TCL language programming

Experience with TSMC N16 technology

Education

Master’s degree in Electrical/Computer Science Engineering

Job description

A leading semiconductor foundry in Austin, TX is seeking a Senior Engineer, Physical Design (ASIC/SoC Place & Route). This role involves the entire APR implementation flow from RTL-to-GDS, working in a hybrid model with 4 days in the office. Candidates should have a Master’s in Electrical/Computer Science Engineering and 7+ years of industry experience, particularly with TSMC technologies. The offered compensation ranges from $106,500 to $162,000 annually, along with comprehensive benefits.