Senior Physical Design Engineer Neuromorphic AI Chips

Intel; Santa Clara (CA); Hybrid; USD 164,000 - 269,000; Full time

Benefits offered by this job

Health benefits

Retirement plan

Vacation

Job summary

Intel seeks a senior physical design engineer to drive integration of chiplet and advanced packaging technologies. You will lead floorplanning, timing constraints, and PnR cycles to meet power and performance targets while collaborating with RTL designers.

Asynchronous design and AI-assisted automation are key growth areas. Applicants should have multi-silicon tape-outs and strong scripting in Perl/TCL/Python, plus Cadence and Synopsys tool experience.

Qualifications

• Bachelor's degree and 6+ years hands-on physical design experience.
• 6+ years setting up floorplans, timing and power constraints, and iterating through synthesis, place and route to meet KPIs.
• 6+ years scripting (Perl, TCL, Python).
• 4+ years debugging FEV and RV reports and ECOs.
• 2+ years chiplet integration/advanced packaging.
• 1+ year AI tool flows for tool flows, debugging and productivity.

Responsibilities

• Understand system specifications to drive die-level requirements.
• Architect full-chip floorplans and partition-level floorplans with macro/pin placements.
• Work with RTL designers to define timing constraints; run synthesis and place-and-route; fix violations.
• Run back-annotated VCS+SDF simulations and iterate to meet power/performance targets.
• Write custom scripts and define tool flows to optimize design flows.

Skills

Perl scripting

Python scripting

TCL scripting

C++ skills

Cadence tools

Synopsys tools

Asynchronous design

Chiplet integration

AI tool flows

Education

Bachelor's degree

Tools

Cadence (Virtuoso)

Synopsys tools (Fusion Compiler, Primetime)

Job description

Intel seeks a senior physical design engineer to drive integration of chiplet and advanced packaging technologies. You will lead floorplanning, timing constraints, and PnR cycles to meet power and performance targets while collaborating with RTL designers.

Asynchronous design and AI-assisted automation are key growth areas. Applicants should have multi-silicon tape-outs and strong scripting in Perl/TCL/Python, plus Cadence and Synopsys tool experience.