Senior ASIC Physical Design Engineer for AI Accelerators

Socket.dev; United States; Remote; USD 150,000 - 250,000; Full time

Benefits offered by this job

Fully company-paid health insurance

Remote-first culture with home office

Job summary

Positron AI seeks a Senior Physical Design Engineer to drive floorplanning through tapeout for AI accelerators. You will own implementation flows, optimize power, timing and area, and collaborate with RTL, synthesis, DFT and backend teams to achieve world-class PPA.

You will execute Innovus-based flows, lead signoff across timing and power, support tapeout, and apply AI-enabled QoR analyses. 5–8 years in physical design with tapeout on advanced nodes is required.

Qualifications

• 5–8 years of experience in physical design from floorplanning through tapeout.
• Experience contributing to one or more advanced-node tapeouts.
• Strong proficiency in Innovus and/or ICC2 implementation flows.
• Solid knowledge of floorplanning, clock tree synthesis, timing, and power closure.
• Experience supporting signoff across timing, power, and related metrics.

Responsibilities

• Support floorplanning, macro placement, and power planning for AI accelerators.
• Drive clock tree synthesis, place and route, and routing optimization to timing closure.
• Contribute to signoff, EMI/IR, ECOs, and met all signoff requirements.
• Collaborate with backend design services and participate in implementation reviews.

Skills

Physical design

Floorplanning through tapeout

Cross-functional collaboration

AI-enabled QoR analysis

Tools

Innovus

ICC2

Tempus

PrimeTime

Voltus

RedHawk

Calibre

Job description

Positron AI seeks a Senior Physical Design Engineer to drive floorplanning through tapeout for AI accelerators. You will own implementation flows, optimize power, timing and area, and collaborate with RTL, synthesis, DFT and backend teams to achieve world-class PPA.

You will execute Innovus-based flows, lead signoff across timing and power, support tapeout, and apply AI-enabled QoR analyses. 5–8 years in physical design with tapeout on advanced nodes is required.