Physical Design Engineer

Tachyum; Las Vegas (NV); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Competitive salary

Benefits package

Career development

International environment

Bleeding-edge technology

Job summary

Tachyum in Las Vegas seeks a senior IC design engineer to drive ultra-high performance, low-power data-processing chips. You will work with RTL teams to meet aggressive PPA targets and contribute to floorplanning, timing closure, and clock-tree design.

The role requires 5+ years in semiconductor design, Verilog expertise, and experience with Innovus. Strong collaboration skills and willingness to mentor junior engineers are essential.

Qualifications

• 5+ years in high performance semiconductor designs.
• BS or MS degree in Electrical Engineering or Computer Science.
• Verilog knowledge and ASIC design flow understanding.
• Proficiency with Innovus or similar P&R tools.
• Strong communication skills and ability to mentor juniors.

Responsibilities

• Implement ultra-high performance, low power data processing chip.
• Collaborate with RTL designers to meet PPA goals and tradeoffs.
• Floor-planning and placement/routing experiments for better PPA.
• Perform timing closure for very high frequency designs; may hand place logic.
• Define low latency/low skew clock tree methodology.
• Define power grid structures to meet EM/IR goals.
• Create regression scripts to run flows on the grid.

Skills

Strong communication

Mentoring juniors

5+ years experience

Verilog knowledge

ASIC design flow

Logic synthesis

Prototyping

Timing analysis

Floor-planning

Flow automation

Innovus experience

Computer architecture

Learning quickly

Milestone delivery

RTL familiarity

PCIe / Ethernet / DDR4 familiarity

Regression scripting

Education

BS or MS Degree in Electrical Engineering or Computer Science

Tools

Innovus

Perl

Tcl

Python

Job description

Location: Las Vegas, NV

Responsibilities

• Responsible for implementation of ultra-high performance and low power data processing chip
• Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs
• Floor‑planning, experimenting with placement and routing techniques for better PPA
• Do timing closure for very high frequency designs with possible hand placement of logic when needed
• Help define low latency/low skew clock tree methodology/design
• Help define appropriate power grid structures to meet EM/IR goals
• Scripting and automating flows to improve turn‑around times

Qualifications

• Member of core team responsible for the crafting and timely delivery of PD partitions
• Strong communication and interpersonal skills required to work with our global design team
• Successful track record of mentoring junior engineers and interns a plus
• More than 5 years of experience in high performance semiconductor designs
• Verilog knowledge and an understanding of ASIC design flow
• Expertise in logic synthesis, prototyping, timing analysis, floor‑planning
• Expertise in flow automation (Perl, Tcl, Python) and understanding of full PD methodology
• Experience with Innovus on 7nm or lower technology nodes
• A background in computer architecture is desirable
• The ability to learn new technologies and apply that knowledge quickly
• A proven track record demonstrating the ability to meet project milestones and deadlines
• BS or MS Degree in Electrical Engineering or Computer Science
• Familiarity with basic synthesizable RTL designs (flops, fifos Clock domain crossing) is a plus.
• Strong familiarity with any of these protocols: PCie, Ethernet (100G and above), DDR4.
• Ability to create regression scripts to run individual and batch jobs on grid.

Benefits

• Competitive salary and benefits package.
• Opportunities for professional development and advancement.
• International environment and further career progression.
• Getting in touch with bleeding edge technology.
• Collaborative and supportive work environment.