R&D Engineering Scientist

Synopsys; Sunnyvale (CA); Presencial; USD 180.000 - 240.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health benefits

Wellness programs

Financial benefits

Descripción de la vacante

Synopsys, Inc. is seeking an experienced PHY and SerDes architect to own high-speed PAM4 PHY architectures, data-path and clocking, and end-to-end link budgets across transmitter, channel, and receiver.

You will lead calibration strategies across PVT conditions and collaborate with analog, digital, and packaging teams to guarantee IP performance. The role focuses on 112 Gb/s and 224 Gb/s PAM4 links, sign-off, modeling, and silicon bring-up, with a strong emphasis on architecture decisions and

Formación

• Strong architectural knowledge of 112 Gb/s and 224 Gb/s PAM4 serial links.
• Expertise in link budgeting, insertion and return loss, crosstalk, jitter, BER, channel operating margin, and FEC coding gain.
• Deep knowledge of CTLE, FFE, DFE, ADC-DSP, PLL, CDR, adaptation, and calibration.
• Experience with channel and behavioral modeling, process-corner analysis, and analog, digital, and package PPA tradeoffs.
• Silicon bring-up and debug experience using PRBS, loopback, eye scan, and calibration capabilities.
• Demonstrated ability to write clear technical specifications and explain architecture decisions to technical, program, and customer audiences.

Responsabilidades

• Own the PHY architecture, including protocols, data rates, BER, and PPA targets.
• Define data-path and clocking architectures, including modulation, equalization, FEC placement, ADC-DSP, PLL, and CDR.
• Lead calibration and adaptation strategies across process, voltage, temperature, and channel conditions.
• Allocate power, area, performance, and latency across analog, digital, and package components.
• Develop block specifications that engineering teams can implement and verify.
• Close the end-to-end link budget across the transmitter, package, channel, and receiver.
• Define architecture sign-off, modeling, observability, and silicon bring-up requirements, including loopback, PRBS, eye scan, and calibration access.
• Align standards, signal and power integrity, package, and program teams on guaranteed IP performance.

Conocimientos

112 Gb/s PAM4

224 Gb/s PAM4

PPA tradeoffs

Signal integrity

Channel modeling

Calibration techniques

Architecture sign-off

Descripción del empleo

We Are

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips. Join us to transform the future through continuous technological innovation.

You Are

You are an experienced PHY and SerDes architect with deep knowledge of high-speed serial links. You translate complex protocol, channel, and system requirements into implementable architectures while balancing power, performance, area, latency, and reliability. You communicate effectively across analog, digital, signal-integrity, package, program, and customer-facing teams.

What You’ll Be Doing

• Own the PHY architecture, including protocols, data rates, BER, and PPA targets.
• Define data-path and clocking architectures, including modulation, equalization, FEC placement, ADC-DSP, PLL, and CDR.
• Lead calibration and adaptation strategies across process, voltage, temperature, and channel conditions.
• Allocate power, area, performance, and latency across analog, digital, and package components.
• Develop block specifications that engineering teams can implement and verify.
• Close the end-to-end link budget across the transmitter, package, channel, and receiver.
• Define architecture sign-off, modeling, observability, and silicon bring-up requirements, including loopback, PRBS, eye scan, and calibration access.
• Align standards, signal and power integrity, package, and program teams on guaranteed IP performance.

The Impact You Will Have

• Define advanced 112 Gb/s and 224 Gb/s PAM4 PHY architectures.
• Improve first-silicon success through rigorous link budgeting, modeling, and observability.
• Reduce integration risk by establishing clear cross-functional specifications and sign-off criteria.
• Enable differentiated, high-performance interface IP for advanced silicon applications.

What You’ll Need

• Strong architectural knowledge of 112 Gb/s and 224 Gb/s PAM4 serial links.
• Expertise in link budgeting, insertion and return loss, crosstalk, jitter, BER, channel operating margin, and FEC coding gain.
• Deep knowledge of CTLE, FFE, DFE, ADC-DSP, PLL, CDR, adaptation, and calibration.
• Experience with channel and behavioral modeling, process-corner analysis, and analog, digital, and package PPA tradeoffs.
• Silicon bring-up and debug experience using PRBS, loopback, eye scan, and calibration capabilities.
• Demonstrated ability to write clear technical specifications and explain architecture decisions to technical, program, and customer audiences.

Who You Are

• A systems thinker who connects circuit-level decisions to end-to-end link performance.
• A collaborative technical leader who works effectively across disciplines and geographies.
• A clear communicator who translates complex tradeoffs into actionable decisions.
• A pragmatic problem solver focused on quality, performance, and silicon success.

The Team You’ll Be a Part Of

You will join a multidisciplinary team developing advanced high-speed PHY IP. You will collaborate with analog, digital, verification, signal-integrity, power-integrity, package, and silicon-validation teams to deliver measurable and differentiated system performance.

Rewards and Benefits

We offer comprehensive health, wellness, and financial benefits. Our total rewards include monetary and non-monetary offerings. Your recruiter will provide additional details during the hiring process.