Senior Semiconductor Layout Designer - Lead Blocks

Micron Technology, Inc.; San Jose (CA); On-site; USD 97,000 - 194,000; Full time

Benefits offered by this job

Medical/Dental/Vision plans

Paid time off

Paid holidays

Equity and bonuses

Job summary

Micron Technology, Inc. is seeking a Staff Layout Designer to develop and prepare multi-dimensional layouts for advanced memory products. You will verify data integrity and lead major block developments, collaborating with TD, design, verification, and CAD teams across global sites.

You will mentor junior members, optimize layout efficiency with automation, and contribute to globally distributed design/layout projects demanding rigorous design rules and quality layouts.

Qualifications

• AS or AS in Electronics, Electrical Engineering, or a related field plus 10 years of direct experience in semiconductor layout design.
• Strong working knowledge of EDA tools: Cadence Virtuoso, Synopsys, Calibre.
• Strong understanding of design rules and delivering quality layouts.

Responsibilities

• Organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution
• Contribute to group management and technical innovation
• Assign resources, schedule tasks, provide direction, and deliver quality-controlled results
• Contribute to projects in a globally distributed design/layout environment
• Effectively mentor junior team members
• Contribute to the improvement of layout efficiency through the development of automation and new methodologies; Lead, plan, and deliver major blocks and product revisions.

Skills

Layout design

Root-cause analysis

Verbal and written communication

Automation for layout

Cross-functional collaboration

Education

AS or AS in Electronics or Electrical Engineering

BS degree in a related field

Tools

Cadence Virtuoso

Synopsys

Calibre

Job description

Micron Technology, Inc. is seeking a Staff Layout Designer to develop and prepare multi-dimensional layouts for advanced memory products. You will verify data integrity and lead major block developments, collaborating with TD, design, verification, and CAD teams across global sites.

You will mentor junior members, optimize layout efficiency with automation, and contribute to globally distributed design/layout projects demanding rigorous design rules and quality layouts.