Senior PDK Reliability Engineer — Hybrid Role

Intel Corporation; Phoenix (AZ); Hybrid; USD 174,000 - 245,000; Full time

Benefits offered by this job

Amazing Benefits

Hybrid work model

Employee stock purchase program

14 paid holidays

3 weeks paid vacation

4-week sabbatical every 4 years

Job summary

Intel Corporation in Hillsboro, Oregon, with a hybrid work model, seeks a senior engineer to drive design enablement for reliability within PDK, TFM, and IP ecosystems. You will shape PPA- and reliability-focused design rules and collaborate with EDA vendors to deliver robust flows for customer design on Intel Si and package technologies.

The role emphasizes hands‑on PDK development, reliability validation, and cross‑functional collaboration.

Qualifications

• Bachelor’s degree in electrical engineering, physics or a related field and 6+ years of relevant work experience or 4+ years of relevant experience and a master’s degree, or a PhD degree with 2+ years of relevant experience.
• 3+ years’ experience in one of the following areas: PDK development, reliability tool and flow, design for reliability, Circuit, IP and SOC design reliability validation using PDK, EDA tool and flow development.

Responsibilities

• Definition and generation of reliability related PDK design rule and collateral covering all reliability mechanism, QA and benchmarking analysis.
• Drive industry EDA tool and flow enablement in synergy with PDK development, work with internal partners and EDA vendors to deliver competitive TFM to support design reliability verification.
• Competitive analysis and benchmarking technology reliability, plan and deliver industry leading PDK, design rule, design collateral, TFM and IP ecosystem to enable internal and external customer design on Intel technology.

Skills

Communication skills

Teamwork

Attention to detail

Quality improvements

Adaptable

Education

Bachelor’s degree in electrical engineering, physics or related field

Master’s degree in electrical engineering, physics, or related field

PhD with 2+ years of experience

Tools

EDA tool/flow development

PDK development

Reliability tool and flow

Scripting / AI programming

Job description

Intel Corporation in Hillsboro, Oregon, with a hybrid work model, seeks a senior engineer to drive design enablement for reliability within PDK, TFM, and IP ecosystems. You will shape PPA- and reliability-focused design rules and collaborate with EDA vendors to deliver robust flows for customer design on Intel Si and package technologies.

The role emphasizes hands‑on PDK development, reliability validation, and cross‑functional collaboration.