Senior Reliability Engineer - PDK & EDA Innovation

Intel; Folsom (CA); Hybrid; USD 150,000 - 285,000; Full time

Benefits offered by this job

14 paid holidays

3 weeks paid vacation

Employee stock purchase program

Job summary

Intel in Hillsboro, Oregon, seeks an Experienced Reliability Engineer to drive PDK design rules and collateral for reliability across advanced silicon and packaging technologies.

You will partner with internal teams and EDA vendors to deliver robust PDK/TFM content, perform benchmarking, and develop IP ecosystems that enable industry-leading PDKs, design rules, and quality verification for customer designs on Intel technology.

Qualifications

• Minimum Bachelor’s degree in electrical engineering, physics or related field with 6+ years of relevant experience, or 4+ years with a Master’s, or PhD with 2+ years of relevant experience.
• 3+ years in PDK development, reliability tool/flow, design for reliability, or related areas using PDK, EDA tools.

Responsibilities

• Definition and generation of reliability related PDK design rules and collateral.
• Drive industry EDA tool and flow enablement with PDK development to support design reliability verification.
• Benchmarking technology reliability and delivering industry leading PDK, design rules, and IP ecosystem.

Skills

PDK and reliability tooling

EDA tool/flow development

Design for reliability

Education

Bachelor's degree in Electrical Engineering/Physics

Master's degree preferred

Tools

PDK tooling

EDA tools/flows

Job description

Intel in Hillsboro, Oregon, seeks an Experienced Reliability Engineer to drive PDK design rules and collateral for reliability across advanced silicon and packaging technologies.

You will partner with internal teams and EDA vendors to deliver robust PDK/TFM content, perform benchmarking, and develop IP ecosystems that enable industry-leading PDKs, design rules, and quality verification for customer designs on Intel technology.