Senior PDK Reliability Engineer — Hybrid & Impact

Intel; Hillsboro (OR); Hybrid; USD 174,000 - 245,000; Full time

Benefits offered by this job

14 paid holidays per year

3 weeks paid vacation per year

4-week paid sabbatical every four yrs

Job summary

Intel is shaping the future of technology with a focus on reliability design enablement for PDKs and TFMs across leading nodes. The role drives PDK design rule development, quality benchmarks, and collaboration with internal teams and EDA vendors to ensure robust design verification and optimal performance.

The candidate will work in a hybrid model with a strong emphasis on cross-functional communication, risk assessment, and continuous improvement in design reliability for silicon and packaging

Qualifications

• Bachelor's degree in electrical engineering, physics or a related field and 6+ years of relevant work experience or 4+ years with a master's or a PhD with 2+ years.
• 3+ years' experience in PDK development, reliability tool/flow, design for reliability, circuit, IP and SOC design reliability validation.

Responsibilities

• Define and generate reliability-related PDK design rules and collateral covering all reliability mechanisms and benchmarking analysis.
• Drive industry EDA tool and flow enablement in synergy with PDK development and work with partners and vendors to deliver competitive TFMs.
• Deliver industry-leading PDKs, design rules, collateral, and IP ecosystem to enable internal and external design on Intel technology.

Skills

AI scripting

Design communication

Stakeholder management

Team collaboration

Education

Bachelor's degree in electrical engineering, physics or related field

Master's degree in electrical engineering, physics, or related field

Tools

PDK development

EDA tool/flow development

Reliability tool and flow

Job description

Intel is shaping the future of technology with a focus on reliability design enablement for PDKs and TFMs across leading nodes. The role drives PDK design rule development, quality benchmarks, and collaboration with internal teams and EDA vendors to ensure robust design verification and optimal performance.

The candidate will work in a hybrid model with a strong emphasis on cross-functional communication, risk assessment, and continuous improvement in design reliability for silicon and packaging