Senior PDK Reliability Engineer — Hybrid

Intel

Phoenix (AZ)

Hybrid

USD 174,000 - 245,000

Full time

18 hours ago
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Benefits offered by this job

Amazing benefits
Stock purchase program
14 paid holidays
3 weeks paid vacation
4-week sabbatical every 4 years
Employee bonuses (annual)

Job summary

Intel is shaping the future of technology with a focus on AI, analytics, and cloud-to-edge solutions. This role supports reliability design enablement for Intel leading technology nodes, delivering PDKs, rules, IPs, and TFMs to enable customer design on Intel silicon and packaging technologies.

You will drive PDK development, reliability validation, and EDA flow enablement, collaborating across teams to achieve best PPA and reliability co-optimization.

Qualifications

  • Bachelor's degree in electrical engineering, physics or related field with 6+ years of experience or 4+ years with a master's, or a PhD with 2+ years.
  • 3+ years' experience in PDK development, reliability tool/flow, design for reliability, circuit/IP/SOC reliability validation using PDK and EDA tool/flow development.

Responsibilities

  • Define and generate reliability related PDK design rules and collateral covering all reliability mechanisms, QA and benchmarking analyses.
  • Drive industry EDA tool and flow enablement with PDK development, collaborate with internal partners and vendors to deliver competitive TFM.
  • Deliver industry-leading PDK, design rule, collateral, TFM and IP ecosystem to enable internal/external design on Intel technology.

Skills

PDK development
Reliability tools
Design for reliability
SOC design reliability
EDA tool/flow development

Education

Bachelor's degree in electrical engineering
Master's degree or PhD preferred

Tools

EDA tools
PDK tooling

Job description

Intel is shaping the future of technology with a focus on AI, analytics, and cloud-to-edge solutions. This role supports reliability design enablement for Intel leading technology nodes, delivering PDKs, rules, IPs, and TFMs to enable customer design on Intel silicon and packaging technologies.

You will drive PDK development, reliability validation, and EDA flow enablement, collaborating across teams to achieve best PPA and reliability co-optimization.

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