Hybrid Reliability Engineer - PDK & EDA Innovation

Intel Corporation; Phoenix (AZ); Hybrid; USD 150,000 - 285,000; Full time

Benefits offered by this job

14 paid holidays per year

Three weeks paid vacation

Four-week sabbatical every four years

Employee stock purchase program

Job summary

Intel Corporation in the United States (AZ, Phoenix area) seeks a senior reliability/PDK engineer to advance reliability design enablement across PDK, QA, and benchmarking on Intel leading nodes.

The role will drive EDA tool integration with PDK development, collaborating with internal teams and vendors to deliver competitive TFM and IP ecosystems that enable customer design on Intel technology.

Qualifications

• Bachelor’s degree in electrical engineering, physics or a related field and 6+ years of relevant work experience or 4+ years with a master’s or PhD with 2+ years of relevant experience.
• 3+ years’ experience in PDK development, reliability tool/flow, design for reliability, circuit, IP and SOC design reliability validation using PDK, EDA tool and flow development.

Responsibilities

• Definition and generation of reliability related PDK design rule and collateral covering all reliability mechanism, QA and benchmarking analysis.
• Drive EDA tool/flow enablement in synergy with PDK development; collaborate with internal partners and EDA vendors to deliver competitive TFM for design reliability verification.
• Competitive analysis and benchmarking of technology reliability; plan and deliver leading PDK, design rule, design collateral, TFM and IP ecosystem for customer design on Intel technology.

Skills

PDK development

reliability tool/flow

design for reliability

Education

Bachelor’s degree in electrical engineering, physics or related field

Master’s degree or PhD in electrical engineering/physics (preferred)

Tools

PDK development

EDA tool/flow

reliability verification tools

Job description

Intel Corporation in the United States (AZ, Phoenix area) seeks a senior reliability/PDK engineer to advance reliability design enablement across PDK, QA, and benchmarking on Intel leading nodes.

The role will drive EDA tool integration with PDK development, collaborating with internal teams and vendors to deliver competitive TFM and IP ecosystems that enable customer design on Intel technology.