Senior PDK Reliability Engineer - Hybrid & Impactful

Intel

Santa Clara (CA)

Hybrid

USD 174,000 - 245,000

Full time

2 days ago

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Benefits offered by this job

Paid holidays

Vacation days

Sabbatical

Employee stock purchase

Job summary

Intel is seeking a senior reliability/PDK engineer to join the design enablement team. You will shape PDK rules, verify reliability, and collaborate with EDA vendors to deliver robust flows and IP ecosystems.

The role demands hands-on experience with PDK development, reliability verification, and aging phenomena, plus strong collaboration across teams in a hybrid work environment. Intel offers extensive benefits.

Qualifications

Bachelor's degree in electrical engineering, physics or related field and 6+ years of relevant work experience or 4+ years with master's or a PhD with 2+ years of relevant experience.
3+ years' experience in PDK development, reliability tool/flow, design for reliability, Circuit/IP/SOC reliability validation using PDK, EDA tool/flow development.

Responsibilities

Definition and generation of reliability related PDK design rule and collateral covering all reliability mechanism, QA and benchmarking analysis.
Drive industry EDA tool and flow enablement in synergy with PDK development; work with internal partners and EDA vendors to deliver competitive TFM to support design reliability verification.
Competitive analysis and benchmarking tech reliability, plan and deliver industry leading PDK, design rule, design collateral, TFM and IP ecosystem to enable internal and external customer design on Intel technology.