Senior PCB Layout Engineer - AI Compute Boards

MatX Inc.; Mountain View (CA); Hybrid; USD 160,000 - 600,000; Full time

Benefits offered by this job

4 weeks PTO

12 holidays

Up to 3 weeks remote work

Medical insurance (employee & depend.)

Dental & Vision

Life insurance

Professional development budget

Job summary

MatX Inc. is seeking an experienced PCB Layout Engineer to design and deliver high-speed, high-density boards for our AI chip, compute tray, and rack-scale platform. This hands-on role focuses on signal integrity, power integrity, and system performance.

You will own layouts from floorplanning to Gerber release, route PCIe Gen5/6, CXL, 112G/224G interfaces, plan stack-ups, and collaborate with SI/PI engineers. Bring-up and debugging support is expected.

Qualifications

• 7+ years of PCB layout experience on multi-layer boards (20+ layers) for high-performance hardware.
• Strong proficiency in high-speed design: differential routing, impedance control, length matching, via optimization.
• Experience with fine-pitch BGA placement/routing for AI ASICs/GPUs and high-speed interfaces (PCIe Gen5/6, CXL, DDR5, 112G/224G SerDes).

Responsibilities

• Own PCB layout from floorplanning through Gerber release for complex boards.
• Route high-speed differential pairs with impedance control and length matching.
• Plan stack-ups, via structure, and BGA placement for AI ASICs.
• Design PDN with VRMs and decoupling strateg ies, in collaboration with SI/PI engineers.
• Coordinate DFM/DFT requirements and board outline with mechanical teams.
• Lead design reviews with JDM/ODM partners and manage release packages.

Skills

PCB layout

High-speed routing

Cadence Allegro

BGA high-density

Signal integrity

Tools

Cadence Allegro

SI/PI tools

Job description

MatX Inc. is seeking an experienced PCB Layout Engineer to design and deliver high-speed, high-density boards for our AI chip, compute tray, and rack-scale platform. This hands-on role focuses on signal integrity, power integrity, and system performance.

You will own layouts from floorplanning to Gerber release, route PCIe Gen5/6, CXL, 112G/224G interfaces, plan stack-ups, and collaborate with SI/PI engineers. Bring-up and debugging support is expected.