Senior Staff PCB Designer for High-Speed AI Boards

Showcify; United States; Remote; USD 180,000 - 240,000; Full time

Job summary

d-Matrix is seeking a Sr. Staff PCB Design Engineer to lead the layout of AI accelerator cards and system baseboards with 112G SerDes and DDR5/HBM interfaces. You will own the design methodology, automate tasks, and partner with power, ASIC, and manufacturing teams to scale hardware development.

The role focuses on multi-layer (20+ layers) boards, high-density routing, and robust PDN strategies. Strong Cadence Allegro expertise and scripting ability are essential for success.

Qualifications

• BS in Electrical/Electronic Engineering or equivalent practical experience.
• 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators.
• Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching.
• Proven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines.
• Deep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design.
• Proven track record routing 112G SerDes and complex DDR5/HBM interfaces.

Responsibilities

• Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards.
• Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints.
• Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting.
• Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects.
• Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs.
• Drive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups.
• Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production.

Skills

High-speed PCB layout

Cadence Allegro Constraint Manager

SKILL scripting

Python

TCL

HDI/ELIC design

SerDes (112G)

DDR5/HBM interfaces

Power integrity

Education

BS in Electrical/Electronic Engineering

Tools

Cadence Allegro

Cadence Allegro API

Python

TCL

SKILL

Job description

d-Matrix is seeking a Sr. Staff PCB Design Engineer to lead the layout of AI accelerator cards and system baseboards with 112G SerDes and DDR5/HBM interfaces. You will own the design methodology, automate tasks, and partner with power, ASIC, and manufacturing teams to scale hardware development.

The role focuses on multi-layer (20+ layers) boards, high-density routing, and robust PDN strategies. Strong Cadence Allegro expertise and scripting ability are essential for success.