Lead High-Speed PCB Design Engineer – AI Accelerator Boards

D-Matrix Corp.; Santa Clara, Northern (CA, KY); Hybrid; USD 150,000 - 210,000; Full time

Job summary

d-Matrix is seeking a Sr. Staff PCB Design Engineer to lead the layout of 20+ layer AI accelerator boards and system baseboards, delivering clean 112G/224G SerDes signals and robust power delivery.

You will own design methodology, automation, and constraint management while collaborating with power, ASIC, and manufacturing teams to scale hardware development with precision. You will drive stack-up definitions, use Megtron 7/8 materials, and build layout infrastructure from the ground up, shaping

Qualifications

• BS in Electrical/Electronic Engineering or equivalent practical experience.
• 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators.

Responsibilities

• Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards.
• Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints.
• Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting.
• Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects.
• Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs.
• Drive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups.
• Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production.

Skills

Constraint management

Automation scripting

High-speed routing

SerDes design

D2D interconnects

96+ layer boards

Education

BS in Electrical/Electronic Engineering

Tools

Cadence Allegro

Job description

d-Matrix is seeking a Sr. Staff PCB Design Engineer to lead the layout of 20+ layer AI accelerator boards and system baseboards, delivering clean 112G/224G SerDes signals and robust power delivery.

You will own design methodology, automation, and constraint management while collaborating with power, ASIC, and manufacturing teams to scale hardware development with precision. You will drive stack-up definitions, use Megtron 7/8 materials, and build layout infrastructure from the ground up, shaping