Senior Package Engineering Lead - Semiconductors

Rambus; San Jose (CA); Hybrid; USD 129,000 - 239,000; Full time

Benefits offered by this job

Flexible, hybrid work environment

Gym membership

Onsite 3 days/week with up to 2 days 0

Job summary

Rambus is seeking a Principal Package Development Engineer in San Jose, CA to lead early chip-package co-design and drive advanced package solutions across multiple platforms. You will partner with design, SI/PI, test, reliability, and supply chain teams to ensure performance, yield and manufacturability for data‑intensive products.

The role emphasizes collaboration with OSAT partners, material suppliers, and cross‑functional teams to bring new packaging concepts through qualification and ramp.

Qualifications

• Bachelor’s degree in Materials Science, Mechanical, Electrical or Chemical Engineering or related field.
• At least seven years of semiconductor package development experience with successful NPI and ramp.
• Experience developing multiple package types and transitioning to volume production.

Responsibilities

• Lead chip-pack­age co-design and select package technologies for new products.
• Develop package solutions across FCCSP, FCBGA, FCQFN, WLCSP, QFN and related platforms.
• Collaborate with cross-functional teams to translate requirements into package designs.
• Engage with OSATs, substrate, leadframe and material suppliers through design reviews and production ramp.
• Drive qualification planning and execution in partnership with Quality and Reliability.

Skills

Chip design collaboration

OSAT partnerships

Flip-chip, wire-bond, WLP

Organic substrate & leadframe design

High-speed / high-pin-count devices

Signal integrity & power integrity

JEDEC standards knowledge

Project management

Education

Bachelor’s degree in Materials Science/Mechanical/Electrical/Chemical Eng

Master’s or PhD in a related discipline

Tools

Cadence Allegro Package Designer

AutoCAD

Job description

Rambus is seeking a Principal Package Development Engineer in San Jose, CA to lead early chip-package co-design and drive advanced package solutions across multiple platforms. You will partner with design, SI/PI, test, reliability, and supply chain teams to ensure performance, yield and manufacturability for data‑intensive products.

The role emphasizes collaboration with OSAT partners, material suppliers, and cross‑functional teams to bring new packaging concepts through qualification and ramp.