PE Package Engineering

Rambus; San Jose (CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Rambus in San Jose, CA is seeking a Principal Package Development Engineer to lead early chip-package co-design and select package technologies for high-performance products. You will drive cross-functional collaboration with design, SI/PI, Test, Quality, Reliability, Manufacturing, and Supply Chain to deliver reliable, low-defect package solutions.

The role requires deep expertise in semiconductor packaging technologies, qualification methods, and transfer to high-volume production.

Qualifications

• Bachelor’s degree in Materials Science, Mechanical, Electrical, Chemical or related field.
• 7+ years semiconductor package development experience.
• Experience developing multiple semiconductor package types and transitioning to volume production.
• Knowledge of flip-chip, wire-bond, wafer-level, leadframe-based, and organic laminate package technologies.
• Experience with high-speed or high-pin-count semiconductor devices.
• Understanding of SI, PI, thermal, mechanical and reliability considerations in package development.
• Experience with OSAT partners and suppliers.
• Understanding of package-material properties and their impact on manufacturing and reliability.
• Experience with package qualification and reliability methods (temperature cycling, HAST, shock, vibration, thermal characterization).
• Knowledge of JEDEC standards and package-design specs.

Responsibilities

• Lead chip-package co-design and package technology selection for new products.
• Develop package solutions across FCCSP, FCBGA, FCQFN, WLCSP, QFN and related platforms.
• Translate product, die, electrical, thermal, mechanical, reliability, manufacturing, and cost requirements into package designs.
• Collaborate with cross-functional teams throughout the product development lifecycle.
• Evaluate package architecture and material options against performance, cost, manufacturability, yield and schedule.
• Lead engagement with OSAT partners and suppliers through design reviews and production ramp.
• Review package drawings, substrate/leadframe designs, materials, and supplier requirements.
• Identify package-related risks and drive mitigation plans and corrective actions.
• Support thermo-mechanical modeling and correlation activities.
• Drive package qualification planning and execution with Quality and Reliability Engg.
• Support transfer of new package technologies to high-volume manufacturing.
• Improve workflows, design methodologies, supplier engagement models, and roadmaps.
• Document technical decisions and development results.

Skills

Signal integrity

Power integrity

Thermal management

Mechanical reliability

Technical communication

Project management

Cross-functional leadership

Education

Bachelors in Materials Science

Bachelors in Mechanical Engineering

Bachelors in Electrical Engineering

Bachelors in Chemical Engineering

Tools

Cadence Allegro

AutoCAD

Job description

Overview

Rambus, a leading provider of semiconductor products and silicon IP that make data faster and safer, is seeking an exceptional Principal Package Development Engineer to join our Package Engineering team in San Jose, California. In this role, you will collaborate with accomplished engineers and cross‑functional teams to develop high‑performance semiconductor products for data‑intensive applications.

This full‑time position reports to the Director of Package Engineering. You will lead package development activities from early product definition and chip‑package co‑design through qualification and manufacturing ramp. Your work will focus on enabling reliable, high‑yield, cost‑effective, and low‑defect production across multiple package technologies.

You will collaborate with internal engineering teams, outsourced semiconductor assembly and test providers, and material and component suppliers to ensure package performance, qualification, and manufacturing readiness across the Rambus product portfolio.

Rambus offers a flexible, hybrid work environment for most office‑based roles. Employees are encouraged to work onsite an average of at least three days per week, with up to two days of remote work.

Responsibilities

• Lead early chip‑package co‑design and package technology selection for new products.
• Develop package solutions across technologies including FCCSP, FCBGA, FCQFN, WLCSP, QFN, and related package platforms.
• Translate product, die, electrical, thermal, mechanical, reliability, manufacturing, and cost requirements into executable package designs.
• Partner with Chip Design, SI/PI, Product Engineering, Test, Quality, Reliability, Marketing, Supply Chain, and other cross‑functional teams throughout the product development lifecycle.
• Evaluate package architecture and material options against performance, cost, manufacturability, yield, reliability, and schedule requirements.
• Lead technical engagement with OSAT partners and substrate, leadframe, and material suppliers through design reviews, development builds, qualification, and production ramp.
• Review package drawings, substrate and leadframe designs, material selections, design rules, and supplier manufacturing requirements.
• Identify package‑related technical risks and drive mitigation plans, root‑cause investigations, and corrective actions.
• Support thermo‑mechanical modeling and simulation activities, including model development, boundary‑condition definition, correlation, and interpretation of results.
• Drive package qualification planning and execution in collaboration with Quality and Reliability Engineering.
• Support successful transfer of new package technologies and products into high‑volume manufacturing.
• Improve package‑development workflows, design methodologies, supplier engagement models, and technology roadmaps.
• Document technical decisions, design requirements, development results, risks, and lessons learned.

Qualifications

• Bachelor’s degree in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or a related technical discipline.
• At least seven years of semiconductor package development experience, including direct involvement in new product introduction and manufacturing ramp.
• Demonstrated experience developing multiple semiconductor package types and successfully transitioning products into volume production.
• Working knowledge of flip‑chip, wire‑bond, wafer‑level, leadframe‑based, and organic laminate package technologies.
• Experience with high‑speed or high‑pin‑count semiconductor devices.
• Understanding of signal integrity, power integrity, thermal, mechanical, and reliability considerations in package development.
• Strong knowledge of organic substrate and leadframe design, materials, fabrication processes, and manufacturing capabilities.
• Experience working directly with OSAT partners and package‑component or material suppliers.
• Understanding of package‑material properties and their impact on manufacturing and reliability.
• Experience with relevant package qualification and reliability methods, including temperature cycling, HAST, mechanical shock, vibration, thermal characterization, and outgassing assessment.
• Working knowledge of applicable JEDEC standards and package‑design specifications.
• Strong analytical, problem‑solving, project‑management, and technical communication skills.
• Demonstrated ability to lead technical activities across cross‑functional and globally distributed teams.

Preferred Qualifications

• Master’s degree or Ph.D. in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or a related discipline.
• Experience with advanced silicon nodes and complex, high‑performance package architectures.
• Experience using Cadence Allegro Package Designer and AutoCAD.
• Experience with thermal or thermo‑mechanical simulation tools and model correlation.
• Familiarity with package warpage, interconnect fatigue, del