Senior Package Design Engineer

Micron Technology, Inc; Boise (ID); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Paid time-off and holidays

Job summary

Micron Technology, Inc in Boise, Idaho, is looking for a Senior Package Design Engineer. The role involves leading co-design efforts and optimizing package architectures for DRAM products. Candidates should have a Master's degree with relevant experience in substrate design.

The position offers competitive benefits, including medical, dental, vision plans, and paid time off. Join a team focused on innovation and excellence in memory solutions.

Qualifications

• Master's degree with 5+ years or Bachelor's with 10+ years in substrate design.
• Hands-on proficiency with EDA tools.
• Experience in advanced memory substrate design.

Responsibilities

• Lead co-design activities with silicon design teams.
• Define and optimize package architectures for DRAM.
• Collaborate with internal teams and OSAT partners.

Skills

Responsible for co-design activities

Package optimization

Experience with EDA tools

Collaboration with SI and PI teams

Education

Master's degree in relevant field

Tools

Cadence Allegro Package Designer

Siemens/MentorGraphics Xpedition

AutoCAD

Job description

Req ID: JR102229 Senior Package Design Engineer

Micron Technology is a world leader in memory and storage solutions. The Global Design, Simulation, and Substrate team develops advanced semiconductor packaging solutions for memory products including DRAM and NAND. The team collaborates globally with internal assembly sites, technology development teams, and OSAT partners to deliver high‑performance, reliable, and manufacturable package designs across Micron’s product portfolio.

Responsibilities

• Lead co‑design activities by partnering with silicon design teams, Business Units, customers and package architecture teams to define new product concepts, optimize die floorplans, interconnection schemes and package architectures from the earliest stages of chip development.
• Define and optimize package architectures for DRAM products, including substrate stack‑up, die pad‑log optimization, wire‑bond and flip‑chip interconnect schemes, and BEOL/RDL flows for advanced memory packages.
• Lead package layout activities—floorplanning, placement, and high‑density routing—and generate and maintain design databases, package drawings, wire‑bond diagrams, interposer drawings, and manufacturing documentation.
• Partner with electrical and simulation teams to interpret parasitic modeling and validation data, and drive design optimization and material selection decisions. Conduct feasibility studies and DFM reviews to assess and advance designs for performance, manufacturability and reliability.
• Partner with Signal Integrity and Power Integrity teams to incorporate simulation analysis and feedback into package architecture definition and design optimization for high‑speed memory interfaces.
• Collaborate with assembly engineering, internal sites and OSAT/subcontractor partners to conduct package and DFMEA reviews, define and manage Assembly DOEs, and ensure designs meet vendor and HVM specifications.
• Work with substrate suppliers, OSATs, Technology Development and Package Architecture teams to define and advance design rules and routing methodologies for next‑generation packaging solutions.
• Support the design group’s continuous improvement initiatives, including global design alignment, package design rule system development, competitive analysis, package roadmaps, and IP development.

Minimum Qualifications

• Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Science or a related interdisciplinary field with 5+ years of industry experience in advanced memory substrate design, or Bachelor’s degree in a related field with 10+ years of industry experience in advanced memory substrate design.
• Hands‑on proficiency with industry‑standard EDA tools such as Cadence Allegro Package Designer+Integrity3D‑IC Platform, Siemens/MentorGraphics Xpedition tool suite, or equivalent advanced package design tools.
• Experience in advanced memory substrate design, including flip‑chip and wire‑bond interconnects, BEOL/RDL flows, substrate stack‑up and routing for high‑density packages.
• Demonstrated experience partnering with Signal Integrity (SI) and Power Integrity (PI) teams to incorporate simulation analysis and feedback into package architecture definition and design optimization for high‑speed memory interfaces.
• Experience collaborating with OSAT partners, assembly engineering teams and multi‑functional global organizations to deliver package designs through HVM.

Preferred Qualifications

• 10+ years of industry experience in semiconductor package design, with a focus on advanced DRAM packaging technologies such as LPDDR, HBM or GDDR, including experience with TSV‑based stacking, micro‑bump layout and Chip Package Interaction (CPI) analysis.
• Experience leading co‑design engagements with silicon design teams, customers or business units— including die floorplan optimization, interconnection scheme definition and package architecture trade‑off studies for new product concepts.
• Experience with Assembly DOE definition and management, DFMEA reviews, and process/material development in an HVM environment.
• Proficiency with mechanical drawing tools such as AutoCAD (Autodesk Mechanical) and experience generating package, interposer and manufacturing drawings.
• Familiarity with advanced packaging platforms such as 2.5D/3D‑IC, fan‑out wafer‑level packaging and System‑in‑Package and their associated design and manufacturing ecosystems.

Micron offers medical, dental and vision plans, paid family leave, paid time‑off and paid holidays. For additional information regarding the benefit programs available, please see the Benefits Guide.

Equal‑Opportunity Employer

Micron is proud to be an equal‑opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.