Senior Package Design Engineer

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 100,000 - 140,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time-off and holidays

Paid family leave

Job summary

1000 Micron Technology, Inc. is looking for a Senior Package Design Engineer in Boise, Idaho. This role involves leading co-design activities for advanced memory products, partnering with silicon design teams, and ensuring designs meet high-performance requirements.

The successful candidate will have substantial experience in semiconductor package design, ideally with a Master’s degree and proficiency in industry-standard EDA tools. Micron offers comprehensive benefits and a commitment to equal opportunity for all employees.

Qualifications

• Master's degree in a relevant field with 5+ years of experience or Bachelor's degree with 10+ years.
• Hands-on proficiency with EDA tools for package design.
• Experience in advanced memory substrate design.

Responsibilities

• Lead co-design activities with silicon design and architecture teams.
• Define and optimize package architectures for DRAM products.
• Collaborate with multi-functional teams to deliver high-performance solutions.

Skills

EDA tools proficiency

Advanced memory substrate design

Signal Integrity (SI) collaboration

Power Integrity (PI) collaboration

Team collaboration

Education

Master’s degree in Electrical Engineering

Bachelor’s degree in related field

Tools

Cadence® Allegro® Package Designer+

Siemens/MentorGraphics Xpedition

Job description

Job Overview

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Global Design, Simulation, and Substrate team at Micron Technology is a world-class group of engineers developing advanced semiconductor packaging solutions for memory products including DRAM and NAND. The team operates globally, collaborating with internal assembly sites, technology development teams, and external OSAT partners to deliver high-performance, reliable, and manufacturable package designs across Micron’s product portfolio! As a Senior Package Design Engineer, you will lead co-design activities that bridge silicon design, package architecture, and product development for advanced DRAM and memory products targeting applications such as Mobile, Automotive, Artificial Intelligence, Edge/Cloud Computing, and Data Center. During the co-design phase, you will partner with silicon design teams, Business Units, customer-facing teams, and package and product architecture teams to define and drive new product concepts from inception through High Volume Manufacturing (HVM). Be part of the team! You will collaborate with global, multi‑functional teams — including Package Architecture, Technology Development, simulation, and manufacturing — to deliver scalable, high‑performance package solutions that meet electrical, mechanical, thermal, and reliability requirements.

Responsibilities

• Lead co‑design activities by partnering with silicon design teams, Business Units, customers, customer‑facing teams, and package and product architecture teams to define new product concepts, optimize die floorplans, interconnection schemes, and package architectures from the earliest stages of chip development.
• Define and optimize package architectures for DRAM products, including substrate stack‑up, die padlog optimization, wire bond and flip chip interconnect schemes, and BEOL/RDL flows for advanced memory packages.
• Lead package layout activities — including floorplanning, placement, and high‑density routing — and generate and maintain design databases, package drawings, wire bond diagrams, interposer drawings, and manufacturing documentation.
• Partner with electrical and simulation teams to interpret parasitic modeling and validation data, and drive design optimization and material selection decisions; conduct feasibility studies and DFM (Design for Manufacturability) reviews to assess and advance designs for performance, manufacturability, and reliability.
• Partner with Signal Integrity (SI) and Power Integrity (PI) teams to incorporate simulation analysis and feedback into package architecture definition and design optimization for high‑speed memory interfaces.
• Collaborate with assembly engineering, internal sites, and OSAT/subcontractor partners to conduct package and DFMEA reviews, define and manage Assembly DOEs, and ensure designs meet vendor and HVM specifications.
• Work with SBT (Substrate) suppliers, OSATs, Technology Development, and Package Architecture teams to define and advance design rules and routing methodologies for next‑generation packaging solutions.
• Support the design group’s continuous improvement initiatives, including global design alignment, package design rule system development, competitive analysis, package roadmaps, and IP development.

Minimum Qualifications

Master’s degree in Electrical Engineering, Mechanical Engineering, Materials Science, or a related interdisciplinary field with 5+ years of industry experience in advanced memory substrate design, or Bachelor’s degree in a related field with 10+ years of industry experience in advanced memory substrate design. Hands‑on proficiency with industry‑standard EDA tools such as Cadence® Allegro® Package Designer+ / Integrity 3D‑IC Platform, Siemens/MentorGraphics Xpedition tool suite, or equivalent advanced package design tools. Experience in advanced memory substrate design, including flip chip and wire bond interconnects, BEOL/RDL flows, substrate stack‑up, and routing for high‑density packages. Demonstrated experience partnering with Signal Integrity (SI) and Power Integrity (PI) teams to incorporate simulation analysis and feedback into package architecture definition and design optimization for high‑speed memory interfaces. Experience collaborating with OSAT partners, assembly engineering teams, and multi‑functional global organizations to deliver package designs through HVM.

Preferred Qualifications

• 10+ years of industry experience in semiconductor package design, with a focus on advanced DRAM packaging technologies such as LPDDR, HBM, or GDDR, including experience with TSV‑based stacking, micro‑bump layout, and Chip Package Interaction (CPI) analysis.
• Experience leading co‑design engagements with silicon design teams, customers, or business units — including die floorplan optimization, interconnection scheme definition, and package architecture trade‑off studies for new product concepts.
• Experience with Assembly DOE definition and management, DFMEA reviews, and process/material development in an HVM environment.
• Proficiency with mechanical drawing tools such as AutoCAD (Autodesk Mechanical) and experience generating package, interposer, and manufacturing drawings.
• Familiarity with advanced packaging platforms such as 2.5D/3D‑IC, fan‑out wafer‑level packaging (FOWLP), or System‑in‑Package (SiP) and their associated design and manufacturing ecosystems.

Benefits

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Equal Employment Opportunity

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.