Senior NVM Digital Designer – RTL & Architecture

Mythic; Palo Alto (CA); On-site; USD 178,000 - 240,000; Full time

Benefits offered by this job

Equal opportunity employer

Job summary

Mythic is hiring an experienced digital designer to work on the next generation NVM controller for analog compute-in memory technologies. You will design, develop and verify NVM IP and digital controllers, collaborating across circuit, digital, compiler, firmware, and software teams to define architecture and improve RTL methodologies.

The role emphasizes RTL design, full-chip verification, and modeling with Verilog/SystemVerilog and Python, with a highly analytical, cross-disciplinary

Qualifications

• Ph.D. or MS in EE or related field with 3+ years in RTL design and architecture development
• Hands-on experience in full chip digital simulation setup, debugging, and verification
• Familiarity with NVM voltage operation and programming algorithms is a plus
• Understanding of computer architecture fundamentals (pipelines, caches, memory hierarchies) is a plus
• Experience with scheduling fabrics, high-performance interconnects, DMA engines, or memory controllers is a plus
• Proficiency in Verilog/SystemVerilog and RTL coding guidelines; timing constraints and EDA flows

Responsibilities

• Participate in design and verify complete IP macros for Mythic product architecture using NVM technologies
• Contribute to the next generation NVM digital controller
• Define NVM controller architecture, interface, and communications
• Collaborate with NVM circuit designers for RNM, functional, and Verilog models
• Drive verifications of RNM and functional models of NVM circuits
• Improve RTL coding practices and methodologies across teams

Skills

RTL design

microarchitecture

architecture development

Python

Verilog/SystemVerilog

Education

MS/PhD in Electrical Engineering

Tools

Verilog-A

Job description

Mythic is hiring an experienced digital designer to work on the next generation NVM controller for analog compute-in memory technologies. You will design, develop and verify NVM IP and digital controllers, collaborating across circuit, digital, compiler, firmware, and software teams to define architecture and improve RTL methodologies.

The role emphasizes RTL design, full-chip verification, and modeling with Verilog/SystemVerilog and Python, with a highly analytical, cross-disciplinary