Senior NVM Architect for Analog Compute-In-Memory AI

Socket.dev; Palo Alto (CA); On-site; USD 190,000 - 280,000; Full time

Job summary

Mythic in Palo Alto, CA is hiring for an experienced NVM design engineer to advance its analog compute-in-memory platform. You will design and verify NVM circuits and collaborate with back-end and validation teams to accelerate silicon evaluation.

The role requires hands-on experience in NVM design/verification, circuit modeling with Python and Verilog, and strong CAD tool proficiency. A Ph.D. or MS in EE is preferred, with 5–10+ years in industry.

Qualifications

• Ph.D. or MS in Electrical Engineering required.
• 5–10+ years of industrial experience in NVM design/verification.
• Hands-on experience with NVM full-chip simulation and debugging.
• Experience modeling circuits with Python, Verilog-A, SystemVerilog Real Number Modeling.
• Knowledge of memory circuit blocks: decoders, HV switches, charge pumps, regulators, bandgap, sense amps, BIST.

Responsibilities

• Verify IP macros for Mythic product architecture with NVM tech.
• Develop NVM architecture for performance/area.
• Design and verify circuits to handshake with analog blocks.
• Design and verify NVM circuits including HV generator, x-path, y-path.
• RNM and functional model development for verification.
• Verify functional blocks and chip-level interfacing with NVM.
• Collaborate with validation engineers to speed silicon evaluation.
• Coordinate with backend teams for production qualification releases.

Skills

NVM design

NVM verification

Circuit modeling

Python scripting

Education

Ph.D. or MS in Electrical Engineering

Tools

SPICE

Cadence

Verilog simulation

Verilog-A

Job description

Mythic in Palo Alto, CA is hiring for an experienced NVM design engineer to advance its analog compute-in-memory platform. You will design and verify NVM circuits and collaborate with back-end and validation teams to accelerate silicon evaluation.

The role requires hands-on experience in NVM design/verification, circuit modeling with Python and Verilog, and strong CAD tool proficiency. A Ph.D. or MS in EE is preferred, with 5–10+ years in industry.