Senior NVM Design Engineer — Analog Compute-In-Memory

Mythic; Palo Alto (CA); On-site; USD 170,000 - 240,000; Full time

Job summary

Mythic in Palo Alto seeks a senior IC designer for NVM memory circuits. You will design and verify IP macros, participate in NVM architecture, and collaborate with back-end teams to qualify silicon.

The role requires 5–10+ years in EE with hands-on NVM design, Python and Verilog modeling, and strong CAD tool fluency. A Ph.D. or MS in EE is preferred. Compensation ranges from $170,000 to $240,000 per year with benefits.

Qualifications

• Hands-on experience in NVM embedded or NVM product design and verification.
• Modeling circuits using Python, Verilog-A, and SystemVerilog Real Number Modeling.
• Experience with memory-circuit blocks: decoders, HV switches, charge pumps, regulators, bandgaps, sense amps, BIST.
• Strong CAD tools proficiency and semiconductor device physics knowledge.
• Experience across multiple NVM tapeouts, layout supervision, and silicon debugging.

Responsibilities

• Participate in design and verify IP macros for Mythic architecture using NVM tech.
• Involve in NVM architecture for optimum performance and area.
• Design and verify new circuits to handshake with analog computation blocks.
• Design, optimize and verify NVM circuits incl. high voltage generator, x-path, y-path, tests.
• Participate in RNM and functional model of NVM circuits for verification.
• Verify functional blocks and full chip interfacing with NVM design.
• Work with validation engineers to speed silicon evaluation.
• Collaborate with backend teams for production qualification releases.

Skills

NVM design experience

Python scripting

Verilog-A / SystemVerilog modeling

CAD tool fluency

Education

Ph.D. or MS in EE

Tools

Cadence / SPICE

Verilog simulations

Job description

Mythic in Palo Alto seeks a senior IC designer for NVM memory circuits. You will design and verify IP macros, participate in NVM architecture, and collaborate with back-end teams to qualify silicon.

The role requires 5–10+ years in EE with hands-on NVM design, Python and Verilog modeling, and strong CAD tool fluency. A Ph.D. or MS in EE is preferred. Compensation ranges from $170,000 to $240,000 per year with benefits.