Senior NoC & Interconnect RTL Designer – Remote

TylSemi, Inc.; San Jose (CA); Hybrid; USD 150,000 - 190,000; Full time

Job summary

TylSemi, Inc. is building chiplet infrastructure IP for AI/HPC systems. We seek an experienced SoC Fabric micro-architect and RTL designer to define on-chip fabric topologies, data-path routing, and integration of major blocks.

You will own CDC, QoS, and fabric error-handling, coordinating with physical design for timing closure and floorplan implications. Hybrid/On-site in San Jose, CA with remote-USA options.

Qualifications

• 8+ years of digital IC design experience with on-chip interconnect ownership.
• Experience owning NoC or interconnect integration at block-lead level.
• Strong SystemVerilog and RTL design for multi-clock designs.

Responsibilities

• Define on-chip fabric topologies connecting subsystems.
• Specify the data-path fabric for high-bandwidth routes.
• Architect register-access fabric with address decoding & protection.
• Define arbitration and QoS for shared fabric resources.
• Own fabric error-handling architecture.
• Own CDC strategy for clock-domain boundaries.
• Own or review all fabric RTL (bridges, FIFOs, arbiters, decoders, pipeline regs).
• Drive integration assembly: top-level connectivity netlist.
• Coordinate with subsystem leads on interfaces and reset sequencing.
• Define fabric performance model.
• Establish fabric bring-up tests.
• Coordinate with phys design on floorplan implications.

Skills

SystemVerilog

NoC design

AXI4/AXI4-Lite/AXI-Stream

CHI/ACE coherency

CDC design

Top-level integration RTL

Static timing constraints

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Job description

TylSemi, Inc. is building chiplet infrastructure IP for AI/HPC systems. We seek an experienced SoC Fabric micro-architect and RTL designer to define on-chip fabric topologies, data-path routing, and integration of major blocks.

You will own CDC, QoS, and fabric error-handling, coordinating with physical design for timing closure and floorplan implications. Hybrid/On-site in San Jose, CA with remote-USA options.