Senior Mixed-Signal Verification Engineer - Power ICs

TYLsemi; United States; Hybrid; USD 140,000 - 220,000; Full time

Job summary

TylSemi, Inc. is seeking an experienced mixed-signal verification engineer to develop and execute verification plans for high-current IVR designs.

You will build analog behavioral models (Verilog-A/SystemVerilog real-number modeling) for power stages and PDN, and perform analog-digital co-simulation with Cadence and Synopsys tools. You will verify digital control loops, create testbenches, run PVT/regression analyses, and troubleshoot issues at transistor and behavioral levels.

Qualifications

• 5+ years of hands-on experience in mixed-signal verification of power management ICs or analog/mixed-signal SoCs.
• Real Number Modeling (RNM) and Verilog-A behavioral modeling.
• Analog-digital co-simulation (AMS, VCS + Spectre, Xcelium).
• Solid understanding of power converter topologies (buck, multi-phase, 3-level buck, switched-capacitor converters).
• Good knowledge of digital control concepts for power converters (PID controllers, DPWM, digital feedback loops).
• Experience with MATLAB/Simulink for system-level modeling and testbench reference generation.
• Proficiency in SystemVerilog and UVM for digital/mixed-signal testbenches.
• Familiarity with Cadence Virtuoso, Spectre, or Synopsys CustomSim for analog simulation.
• Understanding of analog non-idealities (quantization effects, loop delay, sensor offsets, PDN resonances, inductor non-linearities).
• BSEE / MSEE with 8+ years relevant experience.

Responsibilities

• Develop and execute mixed-signal verification plans for high-current IVR designs.
• Build and maintain analog behavioral models (Verilog-A / SystemVerilog real-number modeling) for power stages, integrated inductors, PDN, and analog blocks.
• Perform analog-digital co-simulation using industry-standard tools (Cadence Xcelium + Spectre, Synopsys VCS + FineSim / CustomSim, or AMS Designer).
• Verify digital control loops
• Create testbenches for key performance metrics: transient response (load steps), loop stability, efficiency, ripple, over-current / over-voltage protection, and startup/shutdown sequences.
• Run regressions across PVT corners, Monte-Carlo analysis, and corner-case scenarios.
• Debug mixed-signal issues at both transistor-level and behavioral level.
• Collaborate closely with analog designers, digital designers, and system engineers to close verification coverage.
• Develop automated verification scripts and improve verification methodology for faster turnaround.
• Support post-silicon validation by correlating simulation results with lab measurements.

Skills

Mixed-signal verification

RNM/Verilog-A modeling

AMS co-simulation

Digital control concepts (PID, DPWM)

MATLAB/Simulink

SystemVerilog/UVM

Verilog-A/real-number modeling

Education

BSEE / MSEE

Tools

Cadence Xcelium

Cadence Spectre

Synopsys VCS

FineSim / CustomSim

AMS Designer

Job description

TylSemi, Inc. is seeking an experienced mixed-signal verification engineer to develop and execute verification plans for high-current IVR designs.

You will build analog behavioral models (Verilog-A/SystemVerilog real-number modeling) for power stages and PDN, and perform analog-digital co-simulation with Cadence and Synopsys tools. You will verify digital control loops, create testbenches, run PVT/regression analyses, and troubleshoot issues at transistor and behavioral levels.