Mixed-Signal Verification Engineer — IP & System Modeling

Jobtailor; Oregon (WI); On-site; USD 110,000 - 150,000; Full time

Job summary

Jobtailor is seeking a seasoned Functional Verification Engineer to verify mixed-signal logic components. The role requires strong VHDL/Verilog/SystemVerilog skills, testbench development, and the ability to debug complex digital and analog interactions.

You will develop IP verification plans, run system simulations, analyze power and timing, and collaborate with design teams to drive reliable silicon pre-silicon validation.

Qualifications

• Bachelor's or Master's degree with related verification experience.
• Digital logic experience required.
• VHDL/Verilog/SystemVerilog experience.
• Testbench development, preferably in OVM/UVM.
• Design debugging skills.
• Equivalent experience through school, internships or work.

Responsibilities

• Perform functional verification of mixed signal logic components, including analog behavioral modeling.
• Develop IP verification plans, test benches, and verification environments for mixed signal microarchitecture specs.
• Execute verification plans and run system simulations to verify designs, analyze power and timing, and uncover bugs.
• Replicate, root-cause, and debug issues in the presilicon environment.
• Implement corrective measures to resolve failing tests.
• Collaborate with digital and analog architects, RTL developers, and physical design teams.
• Improve verification of complex architectural features and meet functional, performance, and power goals.
• Document test plans and drive technical reviews with design and architecture teams.
• Maintain and improve functional verification infrastructure and methodology.

Skills

Functional Verification

VHDL/Verilog/SystemVerilog

Testbench Development

Analog Debug Skills

Analog Behavioral Modeling

IP Verification Plans

System Simulation Models

Power Analysis

Timing Analysis

Root-Cause Analysis

Digital Logic Experience

Real Number Simulation Modeling

Education

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's Degree in those fields

Tools

OVM

UVM

Job description

Jobtailor is seeking a seasoned Functional Verification Engineer to verify mixed-signal logic components. The role requires strong VHDL/Verilog/SystemVerilog skills, testbench development, and the ability to debug complex digital and analog interactions.

You will develop IP verification plans, run system simulations, analyze power and timing, and collaborate with design teams to drive reliable silicon pre-silicon validation.