Senior Mixed-Signal RTL Design Engineer

Intel; Boxborough (MA); On-site; USD 140,000 - 200,000; Full time

Job summary

Intel in Boxborough, MA is seeking a skilled engineer to develop logic design, RTL coding, and simulation for mixed-signal IPs used in full chip designs. The role involves architecture collaboration and integrating analog/digital IP across the RTL-to-GDSII flow.

Ideal candidates have a strong background in Verilog/SystemVerilog, digital logic, and mixed-signal integration, with 7+ years (Bachelor) or 4+ years (Master) of industry experience, and a track record of ensuring design correctness

Qualifications

• Expert-level proficiency in Verilog/SystemVerilog (RTL design).
• Solid digital logic fundamentals.
• Experience integrating analog IP with digital logic.
• Deep knowledge RTL-to-GDSII flow, STA, and CDC.

Responsibilities

• Develop logic design, RTL coding, and simulation for mixed-signal IPs.
• Define architecture and microarchitecture features of the block.
• Apply strategies for mixed-signal designs including analog behavior modeling and circuit simulation.
• Write and optimize mixed-signal logic to meet power, performance, area, and timing goals.
• Ensure design integrity for physical implementation.
• Review verification plans and implementation to confirm design features are verified correctly.
• Resolve and implement corrective measures for failing RTL tests to ensure feature correctness.
• Support SoC customers to ensure high-quality integration of the IP block.

Skills

Verilog/SystemVerilog RTL design

Digital logic fundamentals

Analog/digital IP integration

RTL-to-GDSII flow/STA/CDC

Education

Bachelor's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field

Master's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field

Tools

EDA tools

Job description

Intel in Boxborough, MA is seeking a skilled engineer to develop logic design, RTL coding, and simulation for mixed-signal IPs used in full chip designs. The role involves architecture collaboration and integrating analog/digital IP across the RTL-to-GDSII flow.

Ideal candidates have a strong background in Verilog/SystemVerilog, digital logic, and mixed-signal integration, with 7+ years (Bachelor) or 4+ years (Master) of industry experience, and a track record of ensuring design correctness