Mixed Signal Logic Design Engineer

Intel; Boxborough (MA); On-site; USD 140,000 - 200,000; Full time

Job summary

Intel in Boxborough, MA is seeking a skilled engineer to develop logic design, RTL coding, and simulation for mixed-signal IPs used in full chip designs. The role involves architecture collaboration and integrating analog/digital IP across the RTL-to-GDSII flow.

Ideal candidates have a strong background in Verilog/SystemVerilog, digital logic, and mixed-signal integration, with 7+ years (Bachelor) or 4+ years (Master) of industry experience, and a track record of ensuring design correctness

Qualifications

• Expert-level proficiency in Verilog/SystemVerilog (RTL design).
• Solid digital logic fundamentals.
• Experience integrating analog IP with digital logic.
• Deep knowledge RTL-to-GDSII flow, STA, and CDC.

Responsibilities

• Develop logic design, RTL coding, and simulation for mixed-signal IPs.
• Define architecture and microarchitecture features of the block.
• Apply strategies for mixed-signal designs including analog behavior modeling and circuit simulation.
• Write and optimize mixed-signal logic to meet power, performance, area, and timing goals.
• Ensure design integrity for physical implementation.
• Review verification plans and implementation to confirm design features are verified correctly.
• Resolve and implement corrective measures for failing RTL tests to ensure feature correctness.
• Support SoC customers to ensure high-quality integration of the IP block.

Skills

Verilog/SystemVerilog RTL design

Digital logic fundamentals

Analog/digital IP integration

RTL-to-GDSII flow/STA/CDC

Education

Bachelor's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field

Master's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field

Tools

EDA tools

Job description

Position Overview

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed-signal IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed.

Applies various strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed-signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

Reviews the verification plan and implementation to ensure design features are verified correctly, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.

Key Responsibilities

• Develop logic design, RTL coding, and simulation for mixed-signal IPs including cell libraries, functional units, IP blocks, and subsystems
• Participate in the definition of architecture and microarchitecture features of the block being designed
• Apply strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation
• Write and optimize mixed-signal logic to meet power, performance, area, and timing goals
• Ensure design integrity for physical implementation
• Review verification plans and implementation to confirm design features are verified correctly
• Resolve and implement corrective measures for failing RTL tests to ensure feature correctness
• Support SoC customers to ensure high-quality integration of the IP block

What We're Looking For

• Cross-functional collaboration — ability to work effectively with analog, digital, and physical design teams throughout the design cycle
• Ownership mentality — capable of independently designing and owning mixed-signal subsystems and IP blocks end-to-end
• Strong debugging instincts — skilled at identifying and resolving issues across both analog and digital domains with precision and efficiency

Minimum Qualifications

You must possess one of the following education and experience combinations to be initially considered for this position:

• Bachelor's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with 7+ years of industry experience, OR
• Master's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with 4+ years of industry experience

In Addition, All Candidates Must Have

• Expert-level proficiency in Verilog / SystemVerilog (RTL design)
• Digital logic fundamentals
• Experience integrating analog IP with digital logic
• Deep knowledge of RTL-to-GDSII flow, STA, and CDC
• Familiarity with EDA tools
• Understanding of timing, power, and performance trade-offs

Preferred Qualifications

• Knowledge of Power Delivery and Power Management systems
• Solid understanding of analog/mixed-signal blocks such as ADCs, DACs, PLLs, and regulators
• DFT as it relates to mixed-signal HIP
• Scripting language experience, including Perl, TCL/Tk, or Python
• Experience with mixed-signal simulation
• Strong debugging skills across analog and digital domains

Business Group

The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.